Queue based memory controller

• US 6,496,906 B1
• Filed: 04/30/2001
• Issued: 12/17/2002
• Est. Priority Date: 12/04/1998
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Novak, Stephen T., Waldron, Scott, Peck, John C. Jr.
• Primary Examiner(s): Yoo, Do Hyun
• Assistant Examiner(s): Namazi, Mehdi
• Application Number:
  US09/846,008
• Time in Patent Office: 596 Days
• Field of Search: 711/151, 711/154, 711/158, 711/159, 365/203, 370/355
• US Class Current: 711/154
• CPC Class Codes: G06F 13/1642 with request queuing

Abstract

A memory controller for a computer memory which decodes memory requests into individual primitive memory operations which are then queued into separate operation queues. The operation queues independently issue their queued primitive memory operations to the memory in order to initiate the memory request. The operation queues monitor and adhere to timing and ordering dependencies between the primitive memory operations that are queued and those that have already been transmitted to the memory. Once a primitive memory operation is transmitted to the memory, it is dequeued from its respective operation queue. A control queue monitors the progress of the primitive memory operations transmitted to the memory, completes the initiated memory request and provides timing and ordering dependency data to the operation queues.

Claims

1. An apparatus to execute memory requests to a computer memory, said apparatus comprising:

a request decoder operative to receive a memory request and decode said memory request into at least one primitive memory operation, wherein the at least one primitive memory operation comprises one or more of a pre-charge operation and an activation operation;

at least one operation queue coupled to said request decoder operative to store said at least one primitive memory operation for transmission to said computer memory;

a multiplexor coupled to said at least one operation queue and said computer memory and operative to dequeue said at least one primitive memory operation from said at least one operation queue and transmit said at least one primitive memory operation to said computer memory to initiate said memory request; and

at least one control queue coupled to said at least one operation queue and said computer memory and operative to complete said memory request.

2. The apparatus of claim 1 wherein said at least one operation queue is further operative to generate a ready signal to said multiplexor indicating that said at least one operation queue is ready to transmit said at least one primitive memory operation to said computer memory and further wherein said multiplexor is responsive to said ready signal.

3. The apparatus of claim 2 wherein said at least one primitive memory operation comprises dependent ordering data and further wherein said at least one operation queue generates said ready signal from said dependent ordering data.

4. The apparatus of claim 3 wherein said at least one control queue is further operative to generate dependency signals to said at least one operation queue and further wherein said at least one operation queue generates said ready signal from said dependency signals.

5. The apparatus of claim 1 wherein said at least one operation queue, said multiplexor and said at least one control queue are interconnected to share operation dependency data and further wherein said at least one operation queue and said multiplexor are responsive to said operation dependency data.

6. The apparatus of claim 1 wherein said multiplexor selects said at least one primitive memory operation based on a priority selection.

7. The apparatus of claim 1 wherein said at least one primitive memory operation further comprises a read/write operation, and wherein said at least one operation queue is operative to concurrently store primitive memory operations associated with both read and write requests.

8. The apparatus of claim 7 wherein said at least one operation queue comprises an activate queue, a read/write queue and a pre-charge queue.

9. The apparatus of claim 8 wherein said at least one control queue comprises a read control queue and a write control queue.

10. The apparatus of claim 9 wherein said read and write control queues are responsive to said read/write queue and operative to store read/write control data after said read/write primitive memory operations are transmitted to said computer memory.

11. The apparatus of claim 1 wherein said request decoder is implemented as combinational logic.

12. The apparatus of claim 1 wherein said request decoder comprises at least one register coupled to logic operative to decode said memory request into at least one primitive memory operation and store said at least one primitive memory operation into said at least one queue.

13. An apparatus to execute memory requests to a computer memory, said apparatus comprising:

a request decoder operative to receive a memory request and decode said memory request into at least one primitive memory operation, wherein the at least one primitive memory operation comprises one or more of a pre-charge operation, an activation operation and a read/write operation;

at least one operation queue coupled to said request decoder operative to store said at least one primitive memory operation for transmission to said computer memory;

a multiplexor coupled to said at least one operation queue and said computer memory and operative to dequeue said at least one primitive memory operation from said at least one operation queue and transmit said at least one primitive memory operation to said computer memory to initiate said memory request; and

at least one control queue coupled to said at least one operation queue and said computer memory and operative to complete said memory request;

wherein said at least one primitive memory operation comprises activate, read/write and pre-charge;

wherein said at least one operation queue comprises an activate queue, a read/write queue and a pre-charge queue;

wherein said at least one control queue comprises a read control queue and a write control queue; and

wherein said activate queue has a queue depth of 1, said read/write queue has a queue depth of 3 and said pre-charge queue has a queue depth of 1.

14. An apparatus to execute memory requests to a computer memory, said apparatus comprising:

a request decoder operative to receive a memory request and decode said memory request into at least one primitive memory operation, wherein the at least one primitive memory operation comprises one or more of a pre-charge operation, an activation operation and a read/write operation;

at least one operation queue coupled to said request decoder operative to store said at least one primitive memory operation for transmission to said computer memory;

a multiplexor coupled to said at least one operation queue and said computer memory and operative to dequeue said at least one primitive memory operation from said at least one operation queue and transmit said at least one primitive memory operation to said computer memory to initiate said memory request; and

at least one control queue coupled to said at least one operation queue and said computer memory and operative to complete said memory request;

wherein said at least one primitive memory operation comprises activate, read/write and pre-charge;

wherein said at least one operation queue comprises an activate queue, a read/write queue and a pre-charge queue;

wherein said at least one control queue comprises a read control queue and a write control queue; and

wherein said read control queue has a queue depth of twelve and said write control queue has a queue depth of eight.

15. A method for executing memory requests to a computer memory comprising the steps of:

accepting a memory request;

decoding said memory request into at least one primitive memory operation, wherein the at least one primitive memory operation comprises one or more of a pre-charge operation and an activation operation;

queuing said at least one primitive memory operation into at least one operation queue;

selecting said at least one primitive memory operation from said at least one operation queue for transmission to said computer memory;

dequeuing said at least one primitive memory operation from said at least one operation queue;

transmitting said at least one primitive memory operation to said computer memory to initiate said memory request;

queuing control data into at least one control queue;

completing said memory request to said computer memory; and

dequeuing said control data as said memory request completes.

16. The method of claim 15 wherein said at least one primitive memory operation and said control data comprise inter-operation dependencies, said step of selecting further comprising the step of verifying that all inter-operation dependencies have been met.

17. The method of claim 15 wherein said at least one primitive memory operation further comprises a read/write operation, and wherein said at least one operation queue is operative to concurrently store primitive memory operations associated with both read and write requests.

18. The method of claim 15 wherein said at least one control queue comprises a read control queue and a write control queue.

19. A method for executing memory requests to a computer memory comprising the steps of:

accepting a memory request;

decoding said memory request into at least one primitive memory operation, wherein the at least one primitive memory operation comprises one or more of a pre-charge operation, an activation operation and a read/write operation;

queuing said at least one primitive memory operation into at least one operation queue;

selecting said at least one primitive memory operation from said at least one operation queue for transmission to said computer memory;

dequeuing said at least one primitive memory operation from said at least one operation queue;

transmitting said at least one primitive memory operation to said computer memory to initiate said memory request;

queuing control data into at least one control queue;

completing said memory request to said computer memory; and

dequeuing said control data as said memory request completes;

wherein said at least one primitive memory operation comprises pre-charge, activate and read/write, and further wherein said at least one operation queue comprises a pre-charge queue, an activate queue and a read/write queue; and

wherein said pre-charge queue comprises one queue entry, said activate queue comprises one queue entry and said read/write queue comprises three queue entries.

20. The method of claim 19 further comprising the step of:

detecting that at least one queue entry of said at least one operation queue is available;

wherein said step of queuing said at least one primitive memory operation further comprises the step of checking for an available queue entry.

21. A queue based memory controller for receiving a memory request and completing said memory request to a computer memory, said controller comprising:

at least one operation queue comprising at least one queue entry to hold at least one primitive memory operation;

a request decoder operative to receive said memory request and decode said memory request into said at least one primitive memory operation, wherein the at least one primitive memory operation comprises one or more of a pre-charge operation and an activation operation, and further operative to store said at least one primitive memory operation into said at least one operation queue;

a multiplexor coupled to said at least one operation queue and said computer memory and operative to select said at least one primitive memory operation from said at least one operation queue for transmission to said computer memory to initiate said memory request and further operative to dequeue said selected at least one primitive memory operation; and

at least one control queue coupled to said at least one operation queue and said computer memory and operative to store control data, said control data operative to control completion of said memory request in said memory.

22. The queue based memory controller of claim 21 wherein said at least one operation queue further comprises dependency data for said at least one queue entry and said request decoder is further operative to set said dependency data and further wherein said multiplexor is responsive to said dependency data when selecting said at least one primitive memory operation for transmission.

23. The queue based memory controller of claim 22 wherein said dependency data comprises operation timing dependencies and operation ordering dependencies.

24. The queue based memory controller of claim 23 wherein said at least one control queue and said at least one operation queue are further operative to generate dependency data signals and wherein said at least one operation queue is further responsive to said dependency data signals.

25. The queue based memory controller of claim 21 wherein said at least one primitive memory operation further comprises a read/write operation, and wherein said at least one operation queue is operative to concurrently store primitive memory operations associated with both read and write requests.

26. The queue based memory controller of claim 25 wherein said at least one queue comprises a pre-charge queue, an activate queue and a read/write queue.

27. The queue based memory controller of claim 21 wherein said request decoder is implemented as combinational logic.

28. The queue based memory controller of claim 21 wherein said request decoder comprises at least one register coupled to logic operative to decode said memory request into at least one primitive memory operation and store said at least one primitive memory operation into said at least one queue.

29. A queue based memory controller for receiving a memory request and completing said memory request to a computer memory, said controller comprising:

at least one operation queue comprising at least one queue entry to hold at least one primitive memory operation;

a request decoder operative to receive said memory request and decode said memory request into said at least one primitive memory operation, wherein the at least one primitive memory operation comprises one or more of a pre-charge operation, an activation operation and a read/write operation, and further operative to store said at least one primitive memory operation into said at least one operation queue;

a multiplexor coupled to said at least one operation queue and said computer memory and operative to select said at least one primitive memory operation from said at least one operation queue for transmission to said computer memory to initiate said memory request and further operative to dequeue said selected at least one primitive memory operation; and

at least one control queue coupled to said at least one operation queue and said computer memory and operative to store control data, said control data operative to control completion of said memory request in said memory;

wherein said at least one primitive memory operation comprises pre-charge, activate and read/write;

wherein said at least one queue comprises a pre-charge queue, and activate queue and a read/write queue; and

wherein said pre-charge queue has a queue depth of 1, said activate queue has a queue depth of 1 and said read/write queue has a queue depth of 3.