Multiple processor system with standby sparing

• US 6,496,940 B1
• Filed: 06/07/1995
• Issued: 12/17/2002
• Est. Priority Date: 12/17/1992
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Garcia, David J., Horst, Robert W.
• Primary Examiner(s): Beausoleil, Robert
• Assistant Examiner(s): Bonzo, Bryce P.
• Application Number:
  US08/485,062
• Time in Patent Office: 2,750 Days
• Field of Search: 395/182.02, 395/182.08, 395/182.09, 395/182.11, 395/182.1, 714/4, 714/10, 714/11, 714/12, 714/13
• US Class Current: 714/4.3
• CPC Class Codes: G01R 31/31727 Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922
• CPC Class Codes: G01R 31/318533 using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 11/004 Error avoidance G06F11/07 and subgroups take precedence
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G06F 11/1604 where the fault affects the clock signals of a processing unit and the redundancy is at or within the level of clock signal generation hardware
• CPC Class Codes: G06F 11/1633 using mutual exchange of the output between the redundant processing components
• CPC Class Codes: G06F 11/1645 and the comparison itself uses redundant hardware
• CPC Class Codes: G06F 11/165 with continued operation after detection of the error
• CPC Class Codes: G06F 11/1658 Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit
• CPC Class Codes: G06F 11/167 Error detection by comparing the memory output
• CPC Class Codes: G06F 11/1679 at clock signal level
• CPC Class Codes: G06F 11/1683 at instruction level
• CPC Class Codes: G06F 11/1687 at event level, e.g. by interrupt or result of polling
• CPC Class Codes: G06F 11/1695 which are operating with time diversity
• CPC Class Codes: G06F 11/20 using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
• CPC Class Codes: G06F 11/2043 where the redundant components share a common memory address space
• CPC Class Codes: G06F 11/2097 maintaining the standby controller/processing unit updated initialisation or re-synchronisation thereof G06F11/1658 and subgroups
• CPC Class Codes: G06F 11/2736 using a dedicated service processor for test
• CPC Class Codes: G06F 12/0815 : Cache consistency protocols
• CPC Class Codes: G06F 12/1483 : using an access-table, e.g. matrix or list
• CPC Class Codes: G06F 2201/845 : Systems in which the redundancy can be transformed in increased performance
• CPC Class Codes: H04L 12/56 : Packet switching systems
• CPC Class Codes: H04L 47/10 : Flow control; Congestion control
• CPC Class Codes: H04L 49/90 : Buffering arrangements
• CPC Class Codes: H04L 49/901 : using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9057 : Arrangements for supporting packet reassembly or resequencing
• CPC Class Codes: H04L 69/40 : for recovering from a failure of a protocol instance or entity, e.g. service redundancy protocols, protocol state redundancy or protocol service redirection management of faults, events, alarms or notifications in data switching networks H04L41/06

Abstract

A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

Claims

1. A multiple processing system, comprising:

N central processing units where N is an integer greater than or equal to 3, each central processing unit comprising a plurality of processors;

a plurality of input/output devices; and

a network interconnecting each of the N central processing units and the input/output devices so that any one of the N central processing units has separate and independent communicative access to any one of the input/output devices, the network further providing interprocessor communication between the N central processing units, the network including a plurality of routing devices, at least one of the routing devices synchronizing communications for one of the central processing units to enable lockstep operation within said one of the central processing units;

whereby operational tasks of a failed one of the N central processing units employing a one of the input/output devices are performed by any of the other N central processing units including employment of the one of the input/output devices.

2. The system of claim 1, wherein message data is conveyed by multi-bit message packets.

3. The system of claim 2, wherein each of the multi-bit message packets contains information identifying the source of the message data.

4. The system of claim 3, wherein the information further identifies the destination of the message data.

5. The system of claim 4, wherein each of the plurality of routing devices includes a plurality of ports for receiving and transmitting message packets, the routing means including means for routing a message packet received at one of the plurality of ports to another of the plurality of ports according to the information.

6. A multiple processing system, comprising:

N central processing units, including a first central processing unit and a second central processing unit and N being an integer greater than 2, each central processing unit comprising a plurality of processors, each of the N central processing units operating to execute one or more processes;

a primary process executing on the first central processing unit;

a backup process associated with the second central processing unit, the backup process being substantially identical in operation and function to the primary process;

a plurality of input/output devices; and

a network interconnecting the N central processing units and the plurality of input/output devices so that any one of the N central processing units has separate and independent communicative access to any one of the input/output devices, the network further providing interprocessor communication between the N central processing units, the network including a plurality of routing devices, at least one of the routing devices synchronizing communications for one of the central processing units to enable lockstep operation within said one of the central processing units.

7. The system of claim 6, wherein periodically during execution of the primary process the first central processor unit communicates check-point message data to a predetermined one of the plurality of input/output devices for storage, the check-point data being indicative of the state of the execution of the primary process.

8. The system of claim 7, wherein in the event of failure of the first central processing unit, the second central processing unit initiates execution of the associated backup process to take over work being performed by the primary process, including retrieving the stored check-point message data from the predetermined one of the plurality of input/output devices, the backup process becoming a new primary process.

9. The system of claim 8, wherein a third one of the N central processor units has associated with it a new backup process that is substantially identical in operation and function to the new primary process.

10. The system of claim 9, wherein periodically during execution of the new primary process the second central processing unit communicates new check-point message data to another predetermined one of the plurality of input/output devices for storage, the new check-point data being indicative of the state of the execution of the new primary process.