Semiconductor integrated circuit device, method of manufacturing the device, and computer readable medium

• US 6,496,952 B1
• Filed: 09/20/1999
• Issued: 12/17/2002
• Est. Priority Date: 09/25/1998
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd.
• Inventors: Osada, Kenichi, Yano, Kazuo, Ishibashi, Koichiro, Honmura, Tetsuro
• Primary Examiner(s): Ton, David
• Assistant Examiner(s): LAMARRE, GUY J
• Application Number:
  US09/399,330
• Time in Patent Office: 1,184 Days
• Field of Search: 714/724, 714/733, 365/194, 365/200-201, 365/207, 365/222, 365/225.7, 365/49, 365/205, 365/230.06, 365/230.09, 711/105-106, 711/122, 711/167, 711/169
• US Class Current: 714/733
• CPC Class Codes: G11C 15/00 Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
• CPC Class Codes: G11C 2029/0403 during or with feedback to manufacture
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50012 of timing

Abstract

A semiconductor integrated circuit device, a method of manufacturing the device, and a medium for storing a processing procedure for deciding the number of delay circuits built in the device used for designing are disclosed. More particularly, a semiconductor integrated circuit device which guarantees the characteristics of writing into and reading from the built-in memory even when the manufacturing process conditions are varied is obtained. The semiconductor integrated circuit device is provided with a cache memory which includes a BIST circuit composed of a pattern generator, a pattern comparator, and an output register; a register controlled by a register control signal and a register write signal; a variable delay circuit controlled by the register; word lines, and a sense amplifier enable signal line. The timing for enabling the sense amplifier is changed and the memory is measured by the BIST, thereby deciding the optimal timing.

Claims

1. A semiconductor integrated circuit device comprising:

a plurality of bit lines and word lines;

a plurality of memory cells coupled to said bit lines and word lines;

a sense amplifier circuit coupled to said bit lines;

a plurality of delay circuits for delaying a sense amplifier enable signal from a clock signal respectively; and

means for deciding the minimum number of said delay circuits which assures the normal operation of said memory cells with a change of the number of said delay circuits through confirmation of the normal operation of each memory cell.

2. A semiconductor integrated circuit device in accordance with claim 1,

wherein said means for deciding the minimum number of said delay circuits is a CPU which can change the number of said delay circuits, write a predetermined value in each memory cell, read the value written in each memory cell, and compare said read value with said written value, and then decide the minimum number of delay circuits from a result of said confirmation.

3. A semiconductor integrated circuit device in accordance with claim 2, wherein said memory comprises either or both of a cache memory and a DRAM.

4. A semiconductor integrated circuit device in accordance with claim 2, wherein said CPU includes a BIST circuit for testing said memory block;

said BIST circuit comprises;

a pattern generator for generating an address and write data,

a pattern comparator for comparing written data with read data, and

an output register for outputting a result of comparison.

5. A semiconductor integrated circuit device in accordance with claim 1, wherein each of said delay circuits comprises:

an inverter delay circuit; and

a delay circuit number selector circuit.

6. A semiconductor integrated circuit device in accordance with claim 5, wherein said delay circuit number selector circuit comprises:

a register for storing a delay circuit selected number written by said CPU, and

a decoder circuit for reading said delay circuit selected number stored in said register, thereby controlling the number of said inverter delay circuits.

7. A semiconductor integrated circuit device in accordance with claim 1,

wherein said semiconductor integrated circuit device further includes a circuit for fixing the number of delay circuits by blowing a fuse after deciding said minimum number of delay circuits.

8. A semiconductor integrated circuit device in accordance with claim 1,

wherein said semiconductor integrated circuit device further includes means for storing the number of delay circuits in a flash memory after deciding said minimum number of delay circuits.

9. The semiconductor integrated circuit device according claim 1, wherein said memory comprises SRAM memory.