Driving point model utilizing a realizable reduced order circuit for determining a delay of a gate driving an interconnect with inductance

• US 6,496,960 B1
• Filed: 10/27/2000
• Issued: 12/17/2002
• Est. Priority Date: 10/27/2000
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Krauter, Byron Lee, Kashyap, Chandramouli V.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Liu, Andrea
• Application Number:
  US09/697,447
• Time in Patent Office: 781 Days
• Field of Search: 716/1-21
• US Class Current: 716/136
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

A method for determining an equivalent load at the output of a gate driving an interconnect having resistive, inductive and capacitive elements. The method includes modeling the interconnect utilizing a passive driving point model to derive a realizable reduced order circuit for the interconnect. In an advantageous embodiment, the realizable reduced order circuit includes a first resistance parallel-coupled to an inductance and series-coupled to a pi-model equivalent circuit that includes a second resistance and first and second capacitances.

Claims

1. A method for determining an equivalent load at the output of a gate driving an interconnect having resistive, inductive and capacitive elements, said method comprising:

modeling said interconnect utilizing a passive driving point model to derive a realizable reduced order circuit for said interconnect including obtaining the first four moments of an input admittance of said interconnect; and

utilizing said realizable reduced order circuit to determine said equivalent load.

2. The method as recited in claim 1, wherein said equivalent load is an effective capacitance value of said interconnect.

3. The method as recited in claim 2, wherein said utilizing said realizable reduced order circuit includes:

(a) approximating a driving point admittance of said interconnect with said realizable reduced order circuit;

(b) initializing an effective capacitance value of said interconnect to a total capacitance value of said interconnect;

(c) deriving a Thevenin circuit model for said gate;

(d) computing charges delivered by said Thevenin gate model to said effective capacitance and said realizable reduced order circuit;

(e) updating said effective capacitance value by equating an average current drawn by said effective capacitance to an average current drawn by said realizable reduced order circuit; and

(f) repeating (c) through (e) until said effective capacitance value converges.

4. The method as recited in claim 1, wherein said realizable reduced order circuit includes a first resistance parallel-coupled to an inductance and series-coupled to a pi-model equivalent circuit, wherein said pi-model equivalent circuit includes a second resistance and first and second capacitances.

5. The method as recited in claim 1, wherein said first four moments are characterized by:

6. A method for determining a delay at a gate driving an interconnect having resistive, inductive and capacitive elements, said method comprising:

deriving a realizable reduced order circuit of said interconnect utilizing a passive driving point model including obtaining the first four moments of an input admittance of said interconnect;

utilizing said realizable reduced order circuit to determine an equivalent load at the output of said gate; and

determining said delay utilizing said equivalent load.

7. The method as recited in claim 6, wherein said equivalent load is an effective capacitance value of said interconnect.

8. The method as recited in claim 7, wherein said utilizing said realizable reduced order circuit includes:

(a) approximating a driving point admittance of said interconnect with said realizable reduced order circuit;

(b) initializing an effective capacitance value of said interconnect to a total capacitance value of said interconnect;

(c) deriving a Thevenin circuit model for said gate;

(d) computing charges delivered by said Thevenin gate model to said effective capacitance and said realizable reduced order circuit;

(e) updating said effective capacitance value by equating an average current drawn by said effective capacitance to an average current drawn by said realizable reduced order circuit; and

(f) repeating (c) through (e) until said effective capacitance value converges.

9. The method as recited in claim 8, wherein determining said delay includes referring to a lookup table to obtain a precharacterized gate delay value corresponding to said effective capacitance value.

10. The method as recited in claim 6, wherein said realizable reduce order circuit includes a first resistance parallel-coupled to an inductance and series-coupled to a pi-model equivalent circuit, wherein said pi-model equivalent circuit includes a second resistance and first and second capacitances.

11. The method as recited in claim 6, wherein said first four moments are characterized by:

12. A data processing system, comprising:

a processor; and

means for determining a delay at a gate driving an interconnect having resistive, inductive and capacitive elements, said means for determining a delay including;

means for deriving a realizable reduced order circuit of said interconnect utilizing a passive driving point model including obtaining the first four moments of an input admittance of said interconnect;

means for utilizing said realizable reduced order circuit to determine an equivalent load at the output of said gate; and

means for determining said delay utilizing said equivalent load.

13. The data processing system as recited in claim 12, wherein said equivalent load is an effective capacitance value of said interconnect.

14. The data processing system as recited in claim 13, wherein said means for utilizing said realizable reduced order circuit includes:

(a) means for approximating a driving point admittance of said interconnect with said realizable reduced order circuit;

(b) means for initializing an effective capacitance value of said interconnect to a total capacitance value of said interconnect;

(c) means for deriving a Thevenin circuit model for said gate;

(d) means for computing charges delivered by said Thevenin gate model to said effective capacitance and said realizable reduced order circuit;

(e) means for updating said effective capacitance value by equating an average current drawn by said effective capacitance to an average current drawn by said realizable reduced order circuit; and

(f) means for repeating (c) through (e) until said effective capacitance value converges.

15. The data processing system as recited in claim 14, wherein said means for determining said delay includes means for referring to a lookup table to obtain a precharacterized gate delay value corresponding to said effective capacitance value.

16. The data processing system as recited in claim 12, wherein said realizable reduced order circuit includes a first resistance parallel-coupled to an inductance and series-coupled to a pi-model equivalent circuit, wherein said pi-model equivalent circuit includes a second resistance and first and second capacitances.

17. The data processing system as recited in claim 12, wherein said first four moments are characterized by:

18. A computer program product, comprising:

a computer-readable medium having stored thereon computer executable instructions for implementing a method for determining a delay at a gate driving an interconnect having resistive, inductive and capacitive elements, said computer executable instructions when executed, perform the steps of;

deriving a realizable reduced order circuit of said interconnect utilizing a passive driving point model including obtaining the first four moments of an input admittance of said interconnect;

utilizing said realizable reduced order circuit to determine an equivalent load at the output of said gate; and

determining said delay utilizing said equivalent load.

19. The computer program product as recited in claim 18, wherein said equivalent load is an effective capacitance value of said interconnect.

20. The computer program product as recited in claim 19, wherein said utilizing said realizable reduce order circuit includes:

(a) approximating a driving point admittance of said interconnect with said realizable reduced order circuit;

(b) initializing an effective capacitance value of said interconnect to a total capacitance value of said interconnect;

(c) deriving a Thevenin circuit model for said gate;

(d) computing charges delivered by said Thevenin gate model to said effective capacitance and said realizable reduced order circuit;

(e) updating said effective capacitance value by equating an average current drawn by said effective capacitance to an average current drawn by said realizable reduced order circuit; and

(f) repeating (c) through (e) until said effective capacitance value converges.

21. The computer program product as recited in claim 20, wherein determining said delay includes referring to a lookup table to obtain a precharacterized gate delay value corresponding to said effective capacitance value.

22. The computer program product as recited in claim 18, wherein said realizable reduced order circuit includes a first resistance parallel-coupled to an inductance and series-coupled to a pi-model equivalent circuit, wherein said pi-model equivalent circuit includes a second resistance and first and second capacitances.

23. The computer program product as recited in claim 18, wherein said first four moments are characterized by: