Programming programmable logic devices using hidden switches

• US 6,496,969 B2
• Filed: 03/27/2001
• Issued: 12/17/2002
• Est. Priority Date: 03/27/2001
• Status: Expired due to Term

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Lattice Semiconductor Corporation
• Inventors: Feng, Wenyi, Ting, Eric, Roy, Michael L., Oswald, William A.
• Primary Examiner(s): Lam, Tuan T.
• Assistant Examiner(s): NGUYEN, LINH M
• Application Number:
  US09/818,257
• Publication Number:
  US 20020174411A1
• Time in Patent Office: 630 Days
• Field of Search: 716/12, 716/13, 716/14, 716/15, 716/16, 716/17, 326/41, 326/47, 326/39
• US Class Current: 716/117
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

A programming tool for programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs), supports the display of hidden-switch connections, in addition to the display of conventional placed-switch, switch-box, and pseudo-arc connections. A hidden-switch connection between two functional elements in the PLD is represented in graphical displays generated by the programming tool as a curve (e.g., a diagonal straight line) from a jumper wire on the first functional element to another jumper wire on the second functional element, where a jumper wire is represented in the graphical display as a wire connected at one end to an pin of the corresponding functional element and unconnected at the other end. A programming tool that supports hidden-switch connections can be used to program FPGAs and other PLDs having architectures that were not previously supported by conventional programming tools that do not support hidden-switch connections.

Claims

1. A method for representing programming for a programmable logic device (PLD), comprising the steps of:

(a) storing a software representation of the PLD; and

(b) generating, based on the software representation of the PLD, a graphical display representing a hidden-switch connection between first and second functional elements in the PLD, wherein, in the graphical display, the hidden-switch connection is represented by a curve from a first jumper wire at a pin of the first functional element to a second jumper wire at a pin of the second functional element, wherein each jumper wire is represented as being connected to the corresponding pin of the corresponding functional element at a first end of the jumper wire and unconnected at a second end of the jumper wire.

2. The invention of claim 1, wherein:

the PLD is an FPGA;

the curve is a diagonal straight line interconnecting the first and second jumper wires; and

each jumper wire is represented as either a horizontal or vertical line segment.

3. The invention of claim 1, wherein the hidden-switch connection is represented in the graphical display without explicitly representing any particular physical switch device that would provide a corresponding physical connection in the PLD.

4. The invention of claim 1, wherein, when the hidden-switch connection is not selected to be displayed, the graphical display retains representations of the first and second jumper wires.

5. The invention of claim 1, wherein jumper wires are represented in the graphical display only if the PLD program has a corresponding hidden-switch connection.

6. The invention of claim 1, wherein the first and second jumper wires do not intersect in the graphical display and do not terminate at a single common functional element.

7. The invention of claim 1, wherein at least one of the first and second functional elements has a greater number of pins than can be represented in the graphical display using conventional wires in which one each conventional wire is terminated at a different pin.

8. The invention of claim 1, wherein:

the PLD is an FPGA;

the curve is a diagonal straight line interconnecting the first and second jumper wires;

each jumper wire is represented as either a horizontal or vertical line segment;

the hidden-switch connection is represented in the graphical display without explicitly representing any particular physical switch device that would provide a corresponding physical connection in the PLD;

when the hidden-switch connection is not selected to be displayed, the graphical display retains representations of the first and second jumper wires;

jumper wires are represented in the graphical display only if the PLD program has a corresponding hidden-switch connection;

the first and second jumper wires do not intersect in the graphical display and do not terminate at a single common functional element; and

at least one of the first and second functional elements has a greater number of pins than can be represented in the graphical display using conventional wires in which one each conventional wire is terminated at a different pin.

9. A machine-readable medium, having encoded thereon program code, wherein, when the program code is executed by a machine, the machine implements a method for representing programming for a programmable logic device (PLD), comprising the steps of:

(a) storing a software representation of the PLD; and

(b) generating, based on the software representation of the PLD, a graphical display representing a hidden-switch connection between first and second functional elements in the PLD, wherein, in the graphical display, the hidden-switch connection is represented by a curve from a first jumper wire at a pin of the first functional element to a second jumper wire at a pin of the second functional element, wherein each jumper wire is represented as being connected to the corresponding pin of the corresponding functional element at a first end of the jumper wire and unconnected at a second end of the jumper wire.

10. The invention of claim 9, wherein:

the PLD is an FPGA;

the curve is a diagonal straight line interconnecting the first and second jumper wires; and

each jumper wire is represented as either a horizontal or vertical line segment.

11. The invention of claim 9, wherein the hidden-switch connection is represented in the graphical display without explicitly representing any particular physical switch device that would provide a corresponding physical connection in the PLD.

12. The invention of claim 9, wherein, when the hidden-switch connection is not selected to be displayed, the graphical display retains representations of the first and second jumper wires.

13. The invention of claim 9, wherein jumper wires are represented in the graphical display only if the PLD program has a corresponding hidden-switch connection.

14. The invention of claim 9, wherein the first and second jumper wires do not intersect in the graphical display and do not terminate at a single common functional element.

15. The invention of claim 9, wherein at least one of the first and second functional elements has a greater number of pins than can be represented in the graphical display using conventional wires in which one each conventional wire is terminated at a different pin.

16. The invention of claim 9, wherein:

the PLD is an FPGA;

the curve is a diagonal straight line interconnecting the first and second jumper wires;

each jumper wire is represented as either a horizontal or vertical line segment;

the hidden-switch connection is represented in the graphical display without explicitly representing any particular physical switch device that would provide a corresponding physical connection in the PLD;

when the hidden-switch connection is not selected to be displayed, the graphical display retains representations of the first and second jumper wires;

jumper wires are represented in the graphical display only if the PLD program has a corresponding hidden-switch connection;

the first and second jumper wires do not intersect in the graphical display and do not terminate at a single common functional element; and

at least one of the first and second functional elements has a greater number of pins than can be represented in the graphical display using conventional wires in which one each conventional wire is terminated at a different pin.