Surface metal balancing to reduce chip carrier flexing

• US 6,497,943 B1
• Filed: 02/14/2000
• Issued: 12/24/2002
• Est. Priority Date: 02/14/2000
• Status: Expired due to Fees

• Current Assignee: Invensas Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Jimarez, Lisa J., Pierson, Mark V., Jimarez, Miguel A.
• Primary Examiner(s): LAM, CATHY FONG FONG
• Application Number:
  US09/503,395
• Time in Patent Office: 1,044 Days
• Field of Search: 428/209, 174/250, 174/255, 174/260, 257/778, 257/779, 257/780, 257/786
• US Class Current: 428/209
• CPC Class Codes: B32B 15/08 of synthetic resin
• CPC Class Codes: B32B 15/20 comprising aluminium or copper B32B15/016 and B32B15/017 take precedence
• CPC Class Codes: B32B 17/10229 Metallic layers sandwiched by dielectric layers
• CPC Class Codes: B32B 2250/40 Symmetrical or sandwich layers, e.g. ABA, ABCBA, ABCCBA
• CPC Class Codes: B32B 2425/00 Cards, e.g. identity cards, credit cards
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/142 Metallic substrates having insulating layers
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H05K 1/0271 Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
• CPC Class Codes: H05K 2201/0949 Pad close to a hole, not surrounding the hole if used for surface mounting H05K1/114
• CPC Class Codes: H05K 2201/09781 Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
• CPC Class Codes: H05K 2201/10674 Flip chip
• CPC Class Codes: H05K 2201/10734 Ball grid array [BGA]; Bump grid array
• CPC Class Codes: H05K 3/4602 characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
• CPC Class Codes: Y10T 428/24917 including metal layer

Abstract

A surface metal balancing structure for a chip carrier, and an associated method of fabrication, to reduce or eliminate thermally induced chip carrier flexing. A substrate, such as a chip carrier made of organic dielectric material, is formed and includes: internal circuitization layers, a plated through hole, and outer layers comprised of an allylated polyphenylene ether. A stiffener ring for mechanically stabilizing the substrate is bonded to an outer portion, such as an outer perimeter portion, of the top surface of the substrate, in light of the soft and conformal organic material of the substrate. The top and bottom surfaces of the substrate have metal structures, such as copper pads and copper circuitization, wherein a surface area (A) multiplied by a coefficient of thermal expansion (C) is greater for the metal structure at the bottom surface than for the metal structure at the top surface. A metal pattern is adjacent to the top surface so as to make the product AC of metal structures at or near the top and bottom surfaces approximately equal. The metal pattern reduces or eliminates flexing of the substrate in an elevated temperature environment, such as during a reflow of solder that couples a semiconductor chip to the substrate.

Claims

1. An electronic structure, comprising:

a substrate including an organic dielectric material and having an internal conductive structure within and through the substrate;

a stiffener ring adhesively coupled to an outer portion of a first surface of the substrate;

a first metal structure, coupled to the first surface of the substrate, and having a surface area A₁ and a coefficient of thermal expansion C₁;

a second metal structure, coupled to a second surface of the substrate, and having a surface area A₂ and a coefficient of thermal expansion C₂, wherein C₂A₂ exceeds C₁A₁, and wherein the internal conductive structure conductively couples the first metal structure to the second metal structure; and

a metal pattern, adjacent to the first surface of the substrate, and having a surface area A₃ and a coefficient of thermal expansion C₃, wherein (C₂A₂−

C₁A₁−

C₃A₃) is less than (C₂A₂−

C₁A₁) in magnitude, and wherein the metal pattern is electrically insulated from any other conductive structure on or within the substrate.

2. The electronic structure of claim 1, wherein the metal pattern is coupled to the first surface of the substrate and is above the first surface.

3. The electronic structure of claim 1, wherein the metal pattern is coupled to the first surface of the substrate and is below the first surface.

4. The electronic structure of claim 1, wherein (C₃A₃+C₁A₁) and C₂A₂ differ in magnitude by no more than about 20%.

5. The electronic structure of claim 4, wherein a temperature of the substrate is between about 183°

C. and about 310°

C., and wherein a bowing of the first surface of the substrate is less than a bowing that would have occurred, by a factor of at least about 2, had the metal pattern not been included in the electronic structure.

6. The electronic structure of claim 5, further comprising a semiconductor chip conductively coupled to the first metal structure.

7. The electronic structure of claim 4, further comprising a semiconductor chip conductively coupled to the first metal structure at all conductive contacts of the semiconductor chip.

8. The electronic structure of claim 1, where in the internal conductive structure includes a plated through hole (PTH), and wherein the substrate further includes:

a thermally conductive layer having first and the second opposing surfaces;

a first and a second dielectric layer positioned on the first and the second opposing surfaces, respectively, of the thermally conductive layer, wherein the first and second dielectric layers each include the organic dielectric material;

a first power plane within the first dielectric layer;

a first signal plane within the first dielectric layer and positioned between the thermally conductive layer and the first power plane;

a second power plane within the second dielectric layer;

a second signal plane within the second dielectric layer and positioned between the thermally conductive layer and the second power plane;

a third dielectric layer positioned on the first dielectric layer at a surface of the first dielectric layer, wherein the third dielectric layer includes a dielectric material characterized by a coefficient of thermal expansion that increases by no more than a factor of about 3 as a temperature of the third dielectric layer increases from just below to just above a glass transition temperature of the third dielectric layer, and wherein the first surface of the substrate includes a surface of the third dielectric layer; and

a fourth dielectric layer positioned on the second dielectric layer, wherein the fourth dielectric layer includes the dielectric material, and wherein the second surface of the substrate includes a surface of the fourth dielectric layer.

9. The electronic structure of claim 8, wherein the metal pattern is coupled to the surface of the first dielectric layer.

10. The electronic structure of claim 8, wherein the dielectric material includes an allylated polyphenylene ether.

11. The electronic structure of claim 8, wherein the first metal structure includes a conductive metal, the second metal structure includes the conductive metal, and the metal pattern includes the conductive metal.

12. The electronic structure of claim 11, wherein the conductive metal includes copper.

13. The electronic structure of claim 8, wherein (C₃A₃+C₁A₁) and C₂A₂differ in magnitude by no more than about 20%.

14. The electronic structure of claim 13, wherein a temperature of the substrate is exceeds about 183°

C. and is less than about 310°

C., and wherein a bowing of the first surface of the substrate does not exceed about one mil.

15. The electronic structure of claim 14, further comprising a semiconductor chip conductively coupled to the first metal structure.

16. The electronic structure of claim 13, further comprising an electronic device conductively coupled to the first metal structure at all conductive contacts of the semiconductor chip, and wherein the semiconductor chip and the first metal structure are at ambient room temperature.

17. The electronic structure of claim 16, wherein the electronic device includes a semiconductor chip.