SOI pass-gate disturb solution

• US 6,498,058 B1
• Filed: 05/24/2000
• Issued: 12/24/2002
• Est. Priority Date: 09/30/1998
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Nowak, Edward J., Bryant, Andres, Tong, Minh H.
• Primary Examiner(s): Picardat, Kevin M.
• Application Number:
  US09/577,549
• Time in Patent Office: 944 Days
• Field of Search: 438/149, 438/151, 438/155, 438/157, 438/190, 438/195, 438/197, 438/211, 438/479, 438/517, 438/156
• US Class Current: 438/151
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0288 using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An SOI pass-gate disturb solution for an N-type MOSFET wherein a resistor is connected between the gate and the body of the FET to eliminate the disturb condition. The FET is fabricated in a substrate having a source, a drain and a gate, wherein the body of the field effect transistor is electrically floating and the transistor is substantially electrically isolated from the substrate. A high resistance path is provided coupling the electrically floating body of the FET to the gate, such that the body discharges to a low state before significant thermal charging can occur when the gate is low, and thus prevents the accumulation of a charge on the body when the transistor is off. The resistance of the high resistance path is preferably approximately 10¹⁰ Ohms−um divided by the width of the pass-gate.

Claims

1. A method of fabricating a field effect transistor, comprising fabricating the field effect transistor in a substrate with a source, a drain and a gate, wherein the body of the field effect transistor is electrically floating and the transistor is substantially electrically isolated from the substrate, and providing a high resistance path coupling the electrically floating body of the field effect transistor to the gate of the field effect transistor.

2. A method of fabricating a field effect transistor as in claim 1, further including providing the resistance of the high resistance path to be approximately 10¹⁰ Ohms−

um divided by the width of the pass-gate.

3. A method of fabricating a field effect transistor as in claim 1, further including providing the value of the high resistance path to be sufficiently high such that current from the gate to the body, when the gate is high and the source and drain are low, is negligible compared to the MOSFET subthreshold current.

4. A method of fabricating a field effect transistor as in claim 1, including fabricating the transistor in SOI MOSFET.

5. A method of fabricating a field effect as in claim 4, further including lessening an increase in standby current in the SOI MOSFET since the low gate potential grounds the body and prevents the threshold voltage (Vt) from dropping due to drain avalanche multiplication of the current charging body.

6. A method of fabricating a field effect transistor as in claim 1, wherein provision of said high-resistance path discharges the body to a low state before significant thermal charging can occur when the gate is low.

7. A method of fabricating a field effect transistor as in claim 6, wherein discharging of said body prevents the accumulation of charge on the body when the transistor is off.