Memory address decode array with vertical transistors
First Claim
1. A method of forming a logic array for a decoder, the method comprising:
- forming an array of pillars of semiconductor material, wherein each pillar includes a first source/drain region, a body region and a second source/drain region that are vertically stacked and that extend outwardly from a substrate;
forming a number of address lines in trenches that separate rows of pillars;
gating selected pillars with the address lines; and
forming output lines, orthogonal to the address lines, that each interconnect the second source/drain regions of pillars in a column of the array so as to implement a selected logic function.
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Abstract
A decoder for a memory device is provided. The decoder array includes a number of address lines and a number of output lines. The address lines and the output lines form an array. A number of vertical transistors are selectively disposed at intersections of output lines and address lines. Each transistor is formed in at least one pillar of semiconductor material that extends outwardly from a working surface of a substrate. The vertical transistors each include source, drain, and body regions. A gate is also formed along at least one side of the at least one pillar and is coupled to one of the number of address lines. The transistors in the array implement a logic function that selects an output line responsive to an address provided to the address lines.
191 Citations
45 Claims
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1. A method of forming a logic array for a decoder, the method comprising:
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forming an array of pillars of semiconductor material, wherein each pillar includes a first source/drain region, a body region and a second source/drain region that are vertically stacked and that extend outwardly from a substrate;
forming a number of address lines in trenches that separate rows of pillars;
gating selected pillars with the address lines; and
forming output lines, orthogonal to the address lines, that each interconnect the second source/drain regions of pillars in a column of the array so as to implement a selected logic function. - View Dependent Claims (2, 3, 4, 5, 6, 7)
providing a semiconductor wafer that includes;
a first source/drain layer on a substrate;
a body layer on the first source/drain layer; and
a second source/drain layer on the body layer;
forming a first set of parallel trenches extending down trough the second source/drain layer, the body layer, and at least a portion of the first source/drain layer; and
forming a second set of parallel trenches orthogonal to the first set that extend down through the second source/drain layer, the body layer, and at least a portion of the first source/drain layer.
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6. The method of claim 1, wherein forming an array of pillars of semiconductor material comprises:
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providing a substrate;
forming a first source/drain layer on the substrate;
forming a body layer on the first source/drain layer;
forming a second source/drain layer on the body layer;
forming a first set of parallel trenches extending down through the second source/drain layer, the body layer, and at least a portion of the first source/drain layer; and
forming a second set of parallel trenches orthogonal to the first set that extend down through the second source/drain layer, the body layer, and at least a portion of the first source/drain layer.
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7. The method of claim 1, wherein forming a number of address lines in trenches that separate rows of pillars and gating selected pillars with the address lines comprises:
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forming a protective oxide layer on vertical sidewalls of trenches between rows of the pillars;
depositing a polysilicon layer on the vertical sidewalls of the trenches;
applying a photoresist layer on the vertical sidewalls of the trenches;
exposing the vertical sidewalls through the photoresist layer to selectively remove portions of the polysilicon layer adjacent to pillars where a transistor is needed to implement a desired logic function;
depositing a gate insulator on the vertical sidewalls at locations where the polysilicon layer was removed; and
depositing N+ polysilicon on the vertical surfaces of the trenches between the rows of the pillars.
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8. A method of forming a logic array, comprising:
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forming an array of pillars in a semiconductor wafer, wherein each pillar provides a vertical transistor that includes;
a first source/drain layer on a substrate;
a body layer on the first source/drain layer; and
a second source/drain layer on the body layer;
implementing a desired logic function by forming address lines in trenches between rows of the pillars and by selectively gating the address lines to the pillars; and
forming output lines that connect the second source/drain layers in columns of the pillars. - View Dependent Claims (9, 10, 11, 12, 13, 14)
providing a semiconductor wafer that includes;
a first source/drain layer on a substrate;
a body layer on the first source/drain layer; and
a second source/drain layer on the body layer;
forming a first set of parallel trenches extending down through the second source/drain layer, the body layer, and at least a portion of the first source/drain layer; and
forming a second set of parallel trenches orthogonal to the first set that extend down through the second source/drain layer, the body layer, and at least a portion of the first source/drain layer.
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10. The method of claim 8, wherein implementing a desired logic function by forming address lines in trenches between rows of the pillars and by selectively gating the address lines to the pillars, comprises:
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forming a protective oxide layer on vertical sidewalls of trenches between rows of the pillars;
depositing a polysilicon layer on the vertical sidewalls of the trenches;
mask programming the vertical sidewalls of the trenches to selectively form gates; and
depositing N+ polysilicon on the vertical surfaces of the trenches between the rows of the pillars.
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11. The method of claim 8, wherein implementing a desired logic function by forming address lines in trenches between rows of the pillars and by selectively gating the address lines to the pillars, comprises:
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forming a protective oxide layer on vertical sidewalls of trenches between rows of the pillars;
depositing a polysilicon layer on the vertical sidewalls of the trenches;
applying a photoresist layer on the vertical sidewalls of the trenches;
exposing the vertical sidewalls through the photoresist layer to selectively remove portions of the polysilicon layer adjacent to pillars where a transistor is needed to implement a desired logic function;
depositing a gate insulator on the vertical sidewalls at locations where the polysilicon layer was removed; and
depositing N+ polysiliron on the vertical surfaces of the trenches between the rows of the pillars.
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12. The method of claim 8, wherein each trench between rows of pillars includes a single address line.
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13. The method of claim 8, wherein each trench between rows of pillars includes two address lines.
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14. The method of claim 8, wherein each trench between rows of pillars includes one address line and one inverse address line.
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15. A method of forming an integrated circuit logic array, comprising:
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providing an array of vertical transistors extending outwardly from a substrate, wherein the transistors include;
a first source/drain layer on a substrate;
a body layer on the first source/drain layer; and
a second source/drain layer on the body layer;
providing address lines in trenches formed between rows of vertical transistors;
selectively gating rows of the vertical transistors to the address lines to implement a desired logic function; and
forming output lines that connect the second source/drain layers in columns of the pillars. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24)
providing a semiconductor wafer that includes;
a first source/drain layer on a substrate;
a body layer on the first source/drain layer; and
a second source/drain layer on the body layer;
forming a first set of parallel trenches extending down through the second source/drain layer, the body layer, and at least a portion of the first source/drain layer; and
forming a second set of parallel trenches orthogonal to the first set that extend down through the second source/drain layer, the body layer, and at least a portion of the first source/drain layer.
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17. The method of claim 15, wherein providing an array of vertical transistors comprises:
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providing a substrate;
forming a first source/drain layer on the substrate;
forming a body layer on the first source/drain layer; and
forming a second source/drain layer on the body layer.
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18. The method of claim 15, wherein providing an array of vertical transistors comprises:
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providing a substrate;
forming a first source/drain layer on the substrate;
forming a body layer on the first source/drain layer;
forming a second source/drain layer on the body layer;
depositing a pad oxide on the second source/drain layer; and
depositing a pad nitride on the pad oxide.
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19. The method of claim 15, wherein selectively gating rows of the vertical transistors to the address lines to implement a desired function comprises mask programming the vertical sidewalls of the trenches to selectively form gates.
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20. The method of claim 15, wherein selectively gating rows of the vertical transistors to the address lines to implement a desired logic function comprises:
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forming a protective oxide layer on vertical sidewalls of the second set of trenches;
depositing a polysilicon layer on the vertical sidewalls of the second set of trenches;
applying a photoresist layer on the vertical sidewalls of the second set of trenches;
exposing the vertical sidewalls through the photoresist layer to selectively remove portions of the polysilicon layer adjacent to pillars where a transistor is needed to implement a desired logic function; and
depositing a gate insulator on the vertical sidewalls at locations where the polysilicon layer was removed.
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21. The method of claim 15, wherein providing address lines in trenches formed between rows of vertical transistors comprises providing a single address line in each trench formed between adjacent rows of vertical transistors.
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22. The method of claim 15, wherein providing address lines in trenches formed between rows of vertical transistors comprises providing two address lines in each trench formed between adjacent rows of vertical transistors.
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23. The method of claim 15, wherein providing address lines in trenches formed between rows of vertical transistors comprises providing one address line and one inverse address line in each trench formed between adjacent rows of vertical transistors.
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24. The method of claim 15, wherein both the first set of parallel trenches and the second set of parallel trenches extend down into the substrate.
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25. A method of forming an integrated circuit decoder, comprising:
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providing a semiconductor wafer that includes;
a first source/drain layer on a substrate;
a body layer on the first source/drain layer; and
a second source/drain layer on the body layer;
forming a first set of parallel trenches extending down through the second source/drain layer, the body layer, and at least a portion of the first source/drain layer;
forming a second set of parallel trenches orthogonal to the first set that extend down through the second source/drain layer, the body layer, and at least a portion of the first source/drain layer;
providing address lines in the second set of trenches;
selectively gating rows of the vertical transistors to the address lines to implement a desired logic function; and
forming output lines that connect the second source/drain layers in columns of the pillars. - View Dependent Claims (26, 27, 28, 29, 30, 31)
forming a protective oxide layer on vertical sidewalls of trenches between rows of the pillars;
depositing a polysilicon layer on the vertical sidewalls of the trenches;
mask programming the vertical sidewalls of the trenches to selectively form gates; and
depositing N+ polysilicon on the vertical surfaces of the trenches between the rows of the pillars.
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28. The method of claim 25, wherein selectively gating rows of the vertical transistors to the address lines comprises:
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forming a protective oxide layer on vertical sidewalls of trenches between rows of the pillars;
depositing a polysilicon layer on the vertical sidewalls of the trenches;
applying a photoresist layer on the vertical sidewalls of the trenches;
exposing the vertical sidewalls through the photoresist layer to selectively remove portions of the polysilicon layer adjacent to pillars where a transistor is needed to implement a desired logic function;
depositing a gate insulator on the vertical sidewalls at locations where the polysilicon layer was removed; and
depositing N+ polysilicon on the vertical surfaces of the trenches between the rows of the pillars.
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29. The method of claim 25, wherein each of the second set of trenches includes a single address line.
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30. The method of claim 25, wherein each of the second set of trenches includes two address lines.
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31. The method of claim 25, wherein each of the second set of trenches includes one address line and one inverse address line.
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32. A method of forming a decoder, comprising:
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providing an array of output lines and address lines; and
forming an array of vertical transistors at the intersection of the output lines and the address lines, wherein each vertical transistor is formed from a pillar of semiconductor material extending outwardly from a substrate to form a source region, a body region and a drain region;
selectively gating the vertical transistors to the address lines to implement a desired logic function; and
connecting the output lines to the drain region of the vertical transistors. - View Dependent Claims (33, 34, 35, 36)
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37. A method for forming an integrated circuit logic array for a decoder, comprising:
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providing a substrate;
forming a first source/drain layer on the substrate;
forming a body layer on the first source/drain layer;
forming a second source/drain layer on the body layer;
forming a first set of trenches;
forming a second set of trenches that are orthogonal to the first set of trenches, wherein the first set and second set of trenches define vertical transistors;
depositing a polysilicon layer on the vertical sidewalls of the second set of trenches;
selectively removing portions of the polysilicon layer adjacent to pillars where one of the transistors is needed to implement a desired logic function;
depositing a gate insulator on the vertical sidewalls of the second set of trenches at locations where the polysilicon layer was removed;
depositing N+ polysilicon on the vertical surfaces of the second set of trenches; and
forming output lines and contacts to connect columns of vertical transistors.
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38. A method of forming a memory device, comprising:
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providing an array of word lines and complementary bit line pairs;
addressably coupling a memory cell at each intersection of a word line and a bit line of a complementary bit line pair;
coupling a sense amplifier to each complementary pair of bit lines;
coupling a column decoder to the sense amplifier so as to implement a logic function that selects one of the complementary pairs of bit lines responsive to an address provided to the column decoder; and
coupling a row decoder to the word lines so as to implement a logic function that selects one of the word line responsive to an address provided to the row decode, including;
forming an array of pillars in a semiconductor wafer, wherein each pillar provides a vertical transistor that includes;
a first source/drain layer on a substrate;
a body layer on the first source/drain layer; and
a second source/drain layer on the body layer;
implementing a desired logic function by forming address lines in trenches between rows of the pillars and by selectively gating the address lines to the pillars; and
forming output lines that connect the second source/drain layers in columns of the pillars. - View Dependent Claims (39, 40, 41, 42, 43, 44, 45)
providing a semiconductor wafer that includes;
a first source/drain layer on a substrate;
a body layer on the first source/drain layer; and
a second source/drain layer on the body layer;
forming a first set of parallel trenches extending down through the second source/drain layer, the body layer, and at least a portion of the first source/drain layer; and
forming a second set of parallel trenches orthogonal to the first set that extend down through the second source/drain layer, the body layer, and at least a portion of the first source/drain layer.
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40. The method of claim 38, wherein implementing a desired logic function by forming address lines in trenches between rows of the pillars and by selectively gating the address lines to the pillars, comprises:
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forming a protective oxide layer on vertical sidewalls of trenches between rows of the pillars;
depositing a polysilicon layer on the vertical sidewalls of the trenches;
mask programming the vertical sidewalls of the trenches to selectively form gates; and
depositing N+ polysilicon on the vertical surfaces of the trenches between the rows of the pillars.
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41. The method of claim 38, wherein implementing a desired logic function by forming address lines in trenches between rows of the pillars and by selectively gating the address lines to the pillars, comprises:
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forming a protective oxide layer on vertical sidewalls of trenches between rows of the pillars;
depositing a polysilicon layer on the vertical sidewalls of the trenches;
applying a photoresist layer on the vertical sidewalls of the trenches;
exposing the vertical sidewalls through the photoresist layer to selectively remove portions of the polysilicon layer adjacent to pillars where a transistor is needed to implement a desired logic function;
depositing a gate insulator on the vertical sidewalls at locations where the polysilicon layer was removed; and
depositing N+ polysilicon on the vertical surfaces of the trenches between the rows of the pillars.
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42. The method of claim 38, wherein each trench between rows of pillars includes a single address line.
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43. The method of claim 38, wherein each trench between rows of pillars includes two address lines.
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44. The method of claim 38, wherein each trench between rows of pillars includes one address line and one inverse address line.
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45. The method of claim 38, further comprising coupling a microprocessor to the memory device to form a computer system.
Specification