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Memory address decode array with vertical transistors

  • US 6,498,065 B1
  • Filed: 08/30/2000
  • Issued: 12/24/2002
  • Est. Priority Date: 08/04/1998
  • Status: Expired due to Term
First Claim
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1. A method of forming a logic array for a decoder, the method comprising:

  • forming an array of pillars of semiconductor material, wherein each pillar includes a first source/drain region, a body region and a second source/drain region that are vertically stacked and that extend outwardly from a substrate;

    forming a number of address lines in trenches that separate rows of pillars;

    gating selected pillars with the address lines; and

    forming output lines, orthogonal to the address lines, that each interconnect the second source/drain regions of pillars in a column of the array so as to implement a selected logic function.

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