Semiconductor device and method of integrating trench structures

• US 6,498,069 B1
• Filed: 10/17/2001
• Issued: 12/24/2002
• Est. Priority Date: 10/17/2001
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Grivna, Gordon
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Blum, David S
• Application Number:
  US09/977,935
• Time in Patent Office: 433 Days
• Field of Search: 438/411, 438/422, 438/619, 438/386, 438/424
• US Class Current: 438/386
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors

Abstract

A method of making a semiconductor device (10) includes filling a plurality of trenches (30, 32-34) in a substrate (11) with a first fill material (40, 42-44) and lined with a first liner material (36-39) to form an isolation structure (50) in a first trench (30). The first fill material and the first liner material are removed from a second trench (33) which is then lined with a second liner material (46) and filled with a second fill material (69) to produce a capacitance to the substrate. The first fill material and the first liner material are removed from a third trench (34), which is filled with the second fill material to form an electrical contact to the substrate. The first fill material is removed from a fourth trench (34) and dielectric material (78) is deposited on the substrate to produce a void (83) in the fourth trench.

Claims

1. A method of making a semiconductor device, comprising the steps of:

filling trenches (30, 32-34) in a semiconductor substrate (11) with a first fill material (40, 42-44), where the trenches are lined with a first liner material (36-39) to form an isolation structure (50) in a first trench (30) of the trenches;

removing the first fill material and the first liner material from a second trench (33) of the trenches for lining the second trench with a second liner material (46);

filling the second trench with a second fill material (69) to produce a capacitance between the second fill material and the semiconductor substrate;

forming a transistor in the semiconductor substrate;

removing the first fill material from a fourth trench of the trenches; and

depositing a dielectric material on the semiconductor substrate to produce a void in the fourth trench.

2. The method of claim 1, wherein the step of removing includes the step of removing the first fill material and the first liner material from a third trench of the trenches, further comprising the step of filling the third trench with the second fill material to form an electrical contact to the semiconductor substrate.

3. The method of claim 1, wherein the step of depositing includes the step of depositing silicon dioxide on the semiconductor substrate.

4. The method of claim 1, wherein the step of removing the first fill material from the fourth trench includes the step of removing undoped polysilicon from the fourth trench after the step of forming a transistor.

5. The method of claim 1, further comprising the step of lining the trenches with the first liner material.

6. The method of claim 5, wherein the step of lining includes the step of growing silicon dioxide along surfaces of the trenches.

7. The method of claim 1, wherein the step of filling includes the step of filling the trenches with undoped polycrystalline silicon.

8. The method of claim 1, wherein the step of removing includes the step of depositing silicon nitride to coat surfaces of the second trench.

9. The method of claim 1, wherein the step of filling includes the step of depositing doped polycrystalline silicon in the second trench to form an electrode of a capacitor.

10. A method of manufacturing an integrated circuit, comprising the steps of:

lining trenches in a substrate with a first dielectric material;

filling the trenches with a first semiconductor material;

removing the first semiconductor material from first and second trenches to provide an electrical path to the substrate with the first trench; and

depositing a second dielectric material on the substrate for sealing an air gap within the second trench that reduces an effective permittivity of the integrated circuit.

11. The method of claim 10, further comprising the steps of:

etching the first dielectric material from the first trench; and

depositing a second semiconductor material in the first trench to contact the electrical path.

12. The method of claim 11, wherein the step of filling includes the step of filling the trenches with an undoped polycrystalline semiconductor material, and the step of depositing the second semiconductor material includes the step of depositing a doped polycrystalline semiconductor material in the first trench.

13. The method of claim 12, wherein the step of filling the trenches with an undoped polycrystalline semiconductor material includes the step of filling the trenches with polysilicon.

14. The method of claim 12, wherein the step of depositing further includes the step of depositing polysilicon in the first trench.

15. The method of claim 10, further comprising the steps of:

removing the first semiconductor material from a third trench of the trenches;

lining the third trench with a third dielectric material; and

filling the third trench with a second semiconductor material.

16. A method of making a semiconductor device, comprising the steps of:

filling first and second trenches in a semiconductor substrate with a first fill material;

etching the first trench to remove the first fill material;

lining the first trench with a second dielectric material to develop a capacitance;

then forming a transistor in the semiconductor substrate; and

then removing the first fill material to form a void in the second trench.

17. The method of claim 16, further comprising the step of depositing a third dielectric material on the semiconductor substrate to seal the void.

18. The method of claim 17, wherein the first fill material and third dielectric materials include silicon dioxide and the second dielectric material includes silicon nitride.