Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners

• US 6,498,074 B2
• Filed: 06/06/2001
• Issued: 12/24/2002
• Est. Priority Date: 10/29/1996
• Status: Expired due to Term

• Current Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Original Assignee: Tru-Si Technologies, Inc.
• Inventors: Savastiouk, Sergey, Siniaguine, Oleg, Halahan, Patrick B.
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Roman, Angel
• Application Number:
  US09/876,888
• Publication Number:
  US 20020013061A1
• Time in Patent Office: 566 Days
• Field of Search: 438/460, 438/462, 438/465, 438/977, 438/700
• US Class Current: 438/460
• CPC Class Codes: H01L 21/304 Mechanical treatment, e.g. grinding, polishing, cutting H01L21/30625 takes precedence
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/441 Deposition of conductive or insulating materials for electrodes
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06593 Mounting aids permanently on device; arrangements for alignment
• CPC Class Codes: H01L 23/482 consisting of lead-in layers inseparably applied to the semiconductor body electrodes H01L29/40
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10158 : at the passive surface
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: Y10S 438/977 : Thinning or removal of substrate

Abstract

A semiconductor wafer is diced before thinning. The wafer is diced only part of the way through, to form grooves which are at least as deep as the final thickness of each chip to be obtained from the wafer. Then the wafer backside is etched with a dry etch, for example, atmospheric pressure plasma etch. The wafer is thinned until the grooves are exposed from the backside. The dry etch leaves the chip'"'"'s backside smooth. After the grooves have been exposed, the dry etch is continued to remove damage from the chip sidewalls and to round the chips'"'"' bottom edges and corners. The grooves'"'"' aspect ratio is large to reduce the lateral etch rate of the chip sidewalls and thus allow more area for on-chip circuitry.

Claims

1. A method for obtaining one or more chips from a semiconductor wafer, the method comprising:

forming an opening in a first surface of the semiconductor wafer on a boundary of the one or more chips, the first surface being on a first side of the semiconductor wafer, wherein the opening does not go through the wafer; and

thinning the wafer with a dry etch to remove material from an entire second side of the wafer at least until the opening becomes exposed on the second side, wherein the dry etch rounds one or more of the edges and/or corners obtained on the second side of the wafer at a location of the opening when the opening becomes exposed.

2. The method of claim 1 wherein at least a portion of the opening is elongated and for at least said portion, a ratio H1/W1≧

0.5, wherein H1 is a depth of the opening at said portion, the depth being measured before the opening is exposed on the second side, and W1 is a width of the opening at said portion, the width being measured at the first surface.

3. The method of claim 2 wherein W1 is at most 100 μ

m.

4. The method of claim 2 wherein W1 is at most 30 μ

m.

5. The method of claim 2 wherein W1 is at most 5 μ

m.

6. The method of claim 2 wherein the opening extends along an entire boundary of at least one chip.

7. The method of claim 1 wherein at least a portion of the opening is elongated, and for at least said portion, a ratio H2/W1≧

0.5, wherein H2 is a final thickness of the wafer and W1 is a width of the opening at said portion, the width being measured at the first surface.

8. The method of claim 7 wherein W1 is at most 100 μ

m.

9. The method of claim 7 wherein W1 is at most 30 μ

m.

10. The method of claim 7 wherein W1 is at most 5 μ

m.

11. The method of claim 7 wherein the opening extends along an entire boundary of at least one chip.

12. The method of claim 1 wherein at least a portion of the opening is elongated, and for at least said portion, a ratio H1/W2≧

0.5, wherein H1 is a depth of the opening at said portion, the depth being measured before the opening is exposed on the second side, and W2 is a minimal distance between a chip obtained from the wafer and an adjacent portion of the wafer at an end of the dry etch.

13. The method of claim 12 wherein the opening extends along an entire boundary of at least one chip.

14. The method of claim 1 wherein a ratio H2/W2≧

0.5, wherein H2 is a final thickness of the wafer and W2 is a minimal distance between a chip obtained from the wafer and an adjacent portion of the wafer at an end of the dry etch.

15. The method of claim 14 wherein the opening extends along an entire boundary of at least one chip.

16. The method of claim 1 wherein the semiconductor wafer comprises circuitry made at the first side of the wafer, the second side is a backside opposite to the first side, and the opening runs along a scribe line on the first side.

17. The method of claim 15 wherein the opening extends along an entire boundary of at least one chip.