Semiconductor devices and methods for manufacturing the same

• US 6,498,090 B2
• Filed: 02/03/2001
• Issued: 12/24/2002
• Est. Priority Date: 02/03/2000
• Status: Expired due to Term

• Current Assignee: 138 East LCD Advancements Limited (Vector Capital Corporation)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Morozumi, Yukio
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Zarneke, David A
• Application Number:
  US09/775,474
• Publication Number:
  US 20010039111A1
• Time in Patent Office: 689 Days
• Field of Search: 438/612, 438/620, 438/622, 438/624, 438/625, 438/626, 438/629, 438/631, 438/642, 438/648, 438/650, 438/686, 438/687, 438/688
• US Class Current: 438/625
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05006 Dual damascene structure
• CPC Class Codes: H01L 2224/05546 Dual damascene structure
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13164 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48624 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48639 Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/48647 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48724 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48739 : Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/48747 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 23/53223 : Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53238 : Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01025 : Manganese [Mn]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01041 : Niobium [Nb]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: Y10T 428/2495 : Thickness [relative or absolute]

Abstract

In a method for manufacturing a semiconductor device in which wiring layers are formed by a damascene method, certain embodiments relate to a manufacturing method and a semiconductor device, in which a bonding pad section having a multiple-layered structure can be formed by a simple method without increasing the number of process steps. One embodiment includes a method for manufacturing a semiconductor device in which at least an uppermost wiring layer is formed by a damascene method. The method includes the following steps of: (a) forming an uppermost dielectric layer 22 in which an uppermost wiring layer is formed; (b) forming a wiring groove for the wiring layer having a specified pattern and an opening section for bonding pad section in the uppermost dielectric layer 22; (c) forming a first conduction layer for the wiring layer; (d) forming a second conduction layer over the first conduction layer, the second conduction layer composed of a different material from a material of the first conduction layer; and (e) planarizing the second conduction layer, the first conduction layer and the dielectric layer, to thereby form a wiring layer 62 composed of the first conduction layer in the wiring groove and a base conduction layer 82 composed of the first conduction layer and an exposed conduction layer 84 composed of the second conduction layer in the opening section for bonding pad section.

Claims

1. A method for manufacturing a semiconductor device in which at least an uppermost wiring layer is formed by a damascene method, the method comprising the steps of:

(a) forming a dielectric layer in which an uppermost wiring layer is formed;

(b) forming a wiring groove for the wiring layer having a specified pattern and an opening section for a bonding pad section in the dielectric layer;

(c) forming a first conduction layer for the wiring layer;

(d) forming a second conduction layer over the first conduction layer, the second conduction layer comprising a different material from that of the first conduction layer; and

(e) removing excess portions of the second conduction layer, the first conduction layer and the dielectric layer to planarize the second conduction layer, the first conduction layer and the dielectric layer, to thereby form a wiring layer having at least the first conduction layer in the wiring groove and a bonding pad section including a base conduction layer of the first conduction layer and an exposed conduction layer of the second conduction layer in the opening section for the bonding pad section.

2. A method for manufacturing a semiconductor device according to claim 1, wherein, in the step (c), the first conduction layer is formed to have a film thickness smaller than a film thickness of the bonding pad section.

3. A method for manufacturing a semiconductor device according to claim 2, wherein, in the step (c), the first conduction layer is formed in a manner to embed the wiring groove therewith.

4. A method for manufacturing a semiconductor device according to claim 1, further comprising, after the step (e), the step of forming a dielectric protection layer, wherein the protection layer is patterned in a manner to have an opening section that exposes the exposed conduction layer of the bonding pad section.

5. A method for manufacturing a semiconductor device according to claim 1, wherein the wiring layer and the bonding pad section are formed by a method selected from the group consisting of a single-damascene method and a dual-damascene method.

6. A method for manufacturing a semiconductor device according to claim 1, wherein

the first conduction layer is formed from a metal layer comprising at least one of aluminum, copper, silver and alloys thereof, and

the second conduction layer is formed from a metal layer comprising at least one of aluminum, gold and alloys thereof.

7. A method for manufacturing a semiconductor device according to claim 1, further comprising, after the step (b), the step of forming a barrier layer over surfaces of the wiring groove and the opening section for the bonding pad.

8. A method for manufacturing a semiconductor device according to claim 1, wherein, in the step (e), the planarization is conducted by a chemical-mechanical polishing.

9. A method for manufacturing a semiconductor device according to claim 1, wherein the wiring groove is formed to have a width of 0.15 μ

m to 10 μ

m, the opening section for the bonding pad is formed to have a diameter of 30 μ

m to 150 μ

m, the first conduction layer is formed to have a thickness of 300 nm to 1000 nm in the bonding pad section beneath the second conduction layer, and the second conduction layer is formed to have a thickness of 100 nm to 500 nm in the bonding pad section.

10. A method for manufacturing a semiconductor device as in claim 9, wherein the first conduction layer is formed to have a thickness of 300 nm to 1000 nm in the bonding pad section beneath the second conduction layer.

11. A method for manufacturing a semiconductor device according to claim 1, further comprising, after forming the wiring groove and the bonding pad opening section, and prior to forming the first conductive layer, forming a barrier layer in the wiring groove and the bonding pad opening section.

12. A method for manufacturing a semiconductor device according to claim 1, wherein the wiring groove is formed to have a width of 0.15 μ

m to 10 μ

m, the bonding pad opening section is formed to have a diameter of 30 μ

m to 150 μ

m, and the second conduction layer is formed to have a thickness of 100 nm to 500 nm in the bonding pad section.

13. A method for forming an upper wiring layer and a bonding pad in a semiconductor device, comprising:

forming an interlayer dielectric layer over a substrate;

forming a mask layer over the interlayer dielectric layer;

forming an upper dielectric layer over the mask layer;

forming an upper wiring layer opening extending through the upper dielectric layer, the mask layer and the interlayer dielectric layer;

forming a bonding pad opening through the upper dielectric layer by etching through the upper dielectric layer;

depositing a first conductive material to simultaneously fill the upper wiring layer opening and partially fill the bonding pad opening; and

depositing a bonding pad layer to fill the bonding pad opening, wherein the bonding pad layer is disposed over at least a portion of the first conductive material in the bonding pad opening; and

planarizing the device so that an upper surface of the first conductive material in the wiring layer opening and an upper surface of the bonding pad layer in the bonding pad opening are at the same level.

14. A method as in claim 13, further comprising forming a barrier layer in the upper wiring layer opening and the bonding pad opening prior to depositing the first conductive material.

15. A method as in claim 14, wherein:

the barrier layer is formed from one of (a) stacked layers of Ti and TiN, (b) stacked layers of Ta and TaN, (c) a single Ti layer, (d) a single Nb layer, and (e) a single WN layer, and;

the first conductive material is formed from at least one element selected from the group consisting of Al and Cu.

16. A method as in claim 13, further comprising, after planarizing the device, forming a protection layer over the upper surface of the first conductive material in the wiring layer opening and over the upper surface of the bonding pad layer in the bonding pad opening;

and forming an opening in the protection layer so that a portion of the bonding pad layer is exposed and the first conductive material remains covered by the protective material.

17. A method as in claim 13, wherein a portion of the first conductive material is in contact with and extends around the bonding pad layer in the bonding pad opening.

18. A method as in claim 13, wherein the bonding pad layer comprises at least two layers of different materials.

19. A method for manufacturing a semiconductor device in which at least one wiring layer is formed by a damascene method, the method comprising:

forming a dielectric layer;

forming a wiring groove in the dielectric layer and forming a bonding pad opening section in the dielectric layer;

forming a first conduction layer in the wiring groove and the bonding pad opening section;

forming a second conduction layer on the first conduction layer, the second conduction layer having a different composition than the first conduction layer; and

planarizing at least one of the second conduction layer, the first conduction layer and the dielectric layer, to thereby form a wiring layer having at least the first conduction layer in the wiring groove and a bonding pad section including a base conduction layer of the first conduction layer and an exposed conduction layer of the second conduction layer in the bonding pad opening section.

20. A method for manufacturing a semiconductor device according to claim 19, wherein the first conduction layer is formed from a metal layer comprising at least one of aluminum, copper, silver and alloys thereof, and the second conduction layer is formed from a metal layer comprising at least one of aluminum, gold and alloys thereof.