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Design information memory for configurable integrated circuits

  • US 6,498,361 B1
  • Filed: 08/26/1998
  • Issued: 12/24/2002
  • Est. Priority Date: 08/26/1998
  • Status: Expired due to Term
First Claim
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1. A method for forming integrated circuits on a wafer that includes a plurality of die regions, comprising the steps of:

  • forming a respective circuit design in each die region in said plurality of die regions, wherein at least two of said circuit designs are distinct from one another;

    forming a memory in each die region in said plurality of die regions, wherein each respective memory is accessible during said method of forming said integrated circuits and subsequent to dicing of said wafer;

    programming into said memory in each die region in said plurality of die regions design information for the respective circuit design in the respective die region; and

    , dicing said wafer into separate said die regions, subsequent to said step of programming.

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