Design information memory for configurable integrated circuits

• US 6,498,361 B1
• Filed: 08/26/1998
• Issued: 12/24/2002
• Est. Priority Date: 08/26/1998
• Status: Expired due to Term

• Current Assignee: Foothills IP LLC
• Original Assignee: Lightspeed Semiconductor Corporation
• Inventors: Osann, Robert Jr.
• Primary Examiner(s): Meier, Stephen D.
• Application Number:
  US09/140,087
• Time in Patent Office: 1,581 Days
• Field of Search: 257/202, 257/401, 438/4, 438/14, 438/15, 438/462, 438/975
• US Class Current: 257/202
• CPC Class Codes: G06F 21/76 in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G11C 16/20 Initialising; Data preset; Chip identification
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: H01L 27/118 Masterslice integrated circuits

Abstract

On a wafer that includes multiple distinct designs in each die region, a memory is included in each die region. The memory stores information specific to the design implemented in the same die region. Such stored information may include a circuit design identifier or a proprietary technology identifier. Such identifiers minimize IC confusion and aid in tracking usage of proprietary technology.

Claims

1. A method for forming integrated circuits on a wafer that includes a plurality of die regions, comprising the steps of:

forming a respective circuit design in each die region in said plurality of die regions, wherein at least two of said circuit designs are distinct from one another;

forming a memory in each die region in said plurality of die regions, wherein each respective memory is accessible during said method of forming said integrated circuits and subsequent to dicing of said wafer;

programming into said memory in each die region in said plurality of die regions design information for the respective circuit design in the respective die region; and

,

dicing said wafer into separate said die regions, subsequent to said step of programming.

2. The method of claim 1, wherein said design information includes a circuit design identifier.

3. The method of claim 2, further comprising the steps of:

dicing said wafer into separate said die regions;

testing one of said die regions, including reading said circuit design identifier from said memory and selecting test patterns that correspond to said design information.

4. The method of claim 1, wherein said design information includes a proprietary technology identifier.

5. The method of claim 1, wherein said step of forming said memory includes the step of mask programming said memory with said design information.

6. A method for forming at least two distinct integrated circuits on a wafer that includes a plurality of die regions, comprising the steps of:

forming a circuit design in each die region in said plurality of die regions, wherein at least two of said circuit designs are distinct;

forming a memory in each die region in said plurality of die regions, wherein each respective memory is accessible during said method of forming said integrated circuits and subsequent to dicing of said wafer;

programming into said memory in each die region in said plurality of die regions a circuit design identifier; and

,

dicing said wafer into separate said die regions, subsequent to said step of programming.

7. A method for forming an integrated circuit, comprising the steps of:

fabricating an IC design on a die in a wafer;

forming a memory in said die, wherein said memory is accessible during said method of forming said integrated circuit and subsequent to dicing said die from said wafer;

programming into said memory in said die proprietary technology information; and

,

dicing said die region from said wafer, subsequent to said step of programming.

8. A method for forming customized integrated circuits, comprising the steps of:

providing a wafer having a plurality of die regions, wherein each of said die regions includes a prefabricated gate array device, said gate array device including a memory, wherein each respective memory is accessible during said method of forming said customized integrated circuits and subsequent to dicing of said wafer;

customizing each prefabricated gate array device to include a specified respective design;

programming each memory to include design information specific to said specified respective design; and

dicing said wafer into separate said die regions, subsequent to said step of programming.

9. The method of claim 8, wherein said design information includes a design identifier.

10. The method of claim 8, wherein said design information includes proprietary technology information.

11. The method of claim 8, wherein said memory is a mask-programmed ROM.

12. A method for forming integrated circuits on a wafer that includes a plurality of die regions, comprising the steps of:

forming a plurality of integrated circuits, where each respective circuit is included in a respective die region in said plurality of die regions;

forming a memory, where each respective memory is included in a respective die region in said plurality of die regions, and wherein each respective memory is accessible during said method of forming said integrated circuits and subsequent to dicing of said wafer;

programming into said memory in each die region in said plurality of die regions design information for the respective circuit design in the respective die region; and

dicing said wafer into separate said die regions.

13. The method of claim 12, wherein said design information includes a circuit design identifier.

14. The method of claim 13, further comprising the steps of:

dicing said wafer into separate said die regions;

testing one of said die regions, including reading said circuit design identifier from said memory and selecting a test pattern that corresponds to said design information.

15. The method of claim 12, wherein said design information includes a proprietary technology identifier.

16. The method of claim 12, wherein said step of forming said memory includes the step of mask programming said memory with said design information.

17. A method for forming at least two distinct integrated circuits on a wafer that includes a plurality of die regions, comprising the steps of:

forming a circuit design in each die region in said plurality of die regions, wherein at least two of said circuit designs are distinct;

forming a mask programmable Read Only Memory (ROM) in each die region in said plurality of die regions, wherein each respective ROM is accessible during said method of forming said integrated circuits and subsequent to dicing of said wafer;

mask programming into said ROM in each die region in said plurality of die regions design information for the respective circuit design in the respective die region; and

,

dicing said wafer into separate said die regions, subsequent to said step of mask programming.

18. The method of claim 17, wherein said design information includes a circuit design identifier.

19. A method for forming at least two distinct integrated circuits on a wafer that includes a plurality of die regions, comprising the steps of:

forming a circuit design in each die region in said plurality of die regions, wherein at least two of said circuit designs are distinct;

mask programming into a mask programmable Read Only Memory (ROM) in each die region in said plurality of die regions design information for the respective circuit design in the respective die region;

dicing said wafer into separate said die regions, subsequent to said step of mask programming; and

,

testing one of said die regions, including reading said circuit design information from said ROM and selecting test patterns that correspond to said design information.

20. The method of claim 19, wherein said design information includes a proprietary technology identifier.