Discrete integrated circuit rectifier device
First Claim
1. A discrete integrated circuit rectifier device, comprising:
- a semiconductor substrate having first and second surfaces and a plurality of pedestals formed on the first surface;
a MOSFET comprising a plurality of parallel connected MOSFET cells formed on the semiconductor substrate, said MOSFET cells controlling current flow between the two surfaces of said substrate;
each MOSFET cell comprising a spacer formed adjacent the side of a pedestal and defining the location of the MOSFET cell relative to the pedestal, a gate, a gate oxide, a contact region of a first conductivity type, a body region of a second conductivity type implant underlying said gate oxide and contact region, and a channel region comprising a portion of said body region underlying substantially all of said gate oxide; and
a common electrically conductive layer shorting the gate and contact regions of the plurality cells.
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Accused Products
Abstract
A power rectifier having low on resistance, fast recovery time and low forward voltage drop. In a preferred embodiment, the present invention provides a power rectifier device employing a vertical device structure, i.e., with current flow between the major surfaces of the discrete device. The device employs a large number of parallel connected cells, each comprising a MOSFET structure with a gate to drain short via a common conductive layer. This provides a low Vf path through the channel regions of the MOSFET cells to the contact metallization on the other side of the integrated circuit. A thin gate structure is formed annularly around pedestal regions on the upper surface of the device and a precisely controlled body implant defines the channel region and allows controllable device characteristics, including gate threshold voltage and Vf.
91 Citations
7 Claims
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1. A discrete integrated circuit rectifier device, comprising:
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a semiconductor substrate having first and second surfaces and a plurality of pedestals formed on the first surface;
a MOSFET comprising a plurality of parallel connected MOSFET cells formed on the semiconductor substrate, said MOSFET cells controlling current flow between the two surfaces of said substrate;
each MOSFET cell comprising a spacer formed adjacent the side of a pedestal and defining the location of the MOSFET cell relative to the pedestal, a gate, a gate oxide, a contact region of a first conductivity type, a body region of a second conductivity type implant underlying said gate oxide and contact region, and a channel region comprising a portion of said body region underlying substantially all of said gate oxide; and
a common electrically conductive layer shorting the gate and contact regions of the plurality cells. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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Specification