Structure and method of semiconductor via testing

• US 6,498,384 B1
• Filed: 12/05/2000
• Issued: 12/24/2002
• Est. Priority Date: 12/05/2000
• Status: Expired due to Fees

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Marathe, Amit P.
• Primary Examiner(s): Lee, Eddie
• Assistant Examiner(s): NGUYEN, JOSEPH H
• Application Number:
  US09/730,984
• Time in Patent Office: 749 Days
• Field of Search: 257/758, 257/751, 257/774, 257/760, 257/211, 257/520, 257/920
• US Class Current: 257/520
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: Y10S 257/92 Conductor layers on different levels connected in parallel, e.g. to reduce resistance

Abstract

A semiconductor wafer having a via test structure is provided which includes a semiconductor substrate having a plurality of semiconductor devices. A dielectric layer deposited over the semiconductor substrate has second and fourth channels unconnected to the plurality of semiconductor devices. A via dielectric layer deposited over the channel dielectric layer has first and second vias and third and fourth vias respectively open to opposite ends of the second channel and the fourth channel. A second dielectric layer over the via dielectric layer has first, third, and fifth channels respectively connected to the first via, the second and third vias, and the fourth via. The first channel, the first via, the second channel, the second via, the third channel, the third via, the fourth channel, the fourth via, and the fifth channel are connected in series and the first and fifth channel are probed to determine the presence or absence of voids in the vias.

Claims

1. A semiconductor wafer having a via test structure comprising:

a semiconductor substrate having a plurality of semiconductor devices;

a first dielectric layer over the semiconductor substrate having a plurality of openings provided therein;

first barrier layers lining the openings;

first conductor cores filling the openings to form second and fourth channels unconnected to the plurality of semiconductor devices;

a via dielectric layer formed over the dielectric layer and having first and second via openings and third and fourth via openings provided therein respectively open to opposite ends of the second channel and the fourth channel;

a second dielectric layer formed over the via dielectric layer and having first, third, and fifth channel openings provided therein respectively open to the first via opening, the second and third via openings, and the fourth via opening;

second barrier layers lining the first, second, third, and fourth via openings and the first, third, and fifth channel openings; and

second conductor cores filling the first, second, third, and fourth via openings and the first, third and fifth channel openings to form first, third, and fifth channels having the first channel, the first via, the second channel, the second via, the third channel, the third via, the fourth channel, the fourth via, and the fifth channel connected in series whereby the first and fifth channels are probed to determine the presence or absence of voids in the vias.

2. The semiconductor wafer as claimed in claim 1 including a capping layer over the second dielectric layer and the first, third, and fifth channel opening whereby the first and fifth channel are exposed to be probed.

3. The semiconductor wafer as claimed in claim 1 wherein the first, second, third, and fourth channels are in-line.

4. The semiconductor wafer as claimed in claim 1 wherein the first and second conductor cores are of a material selected from a group consisting of copper, aluminum, silver, gold, alloys thereof, and combinations thereof.

5. A semiconductor wafer having a via test structure comprising. a silicon substrate having a plurality of semiconductor deices;

a device oxide layer on the semiconductor substrate;

a first oxide layer on the device dielectric and having a plurality of openings provided therein;

first barrier layers lining the plurality of openings;

first seed layers lining the first barrier layers;

first conductor cores filling the openings to form second and fourth channels unconnected to the plurality of semiconductor devices;

a via oxide layer formed over the channel dielectric layer and having first and second via op and third and fourth via openings provided therein respectively open to opposite ends of the second channel and the fourth channel;

a second oxide layer formed over the via dielectric layer and having first, third, and fifth channel openings provided therein respectively open to the first via opening, the second and third via openings, and the fourth via opening;

second barrier layers lining the first, second, third and fourth via openings and the first, third, and fifth channel openings;

second seed layers lining the second barrier layers; and

second conductor cores filling the first, second, third, and fourth via opt and the first, third, and fifth channel opening to form first, third, and fifth channels having the first channel, the first via, the second channel, the second via, the third channel, the third via, the fourth channel, the fourth via, and the fifth channel connected in series whereby the first and fifth channels are probed to determine the presence or absence of voids in the fist, second, third, and fourth vias.

6. The semiconductor wafer as claimed in claim 5 including a capping layer over the second dielectric layer and the first, third, and fifth channel opening whereby the first and fifth channel are exposed to be probed.

7. The semiconductor wafer as claimed in claim 5 wherein the first, second, third, fourth, and fifth channels are in-line and the first, second, third, and fourth vias are in-line.

8. The semiconductor wafer as claimed in claim 5 wherein the seed layers and the first and second. conductor cores are of a material selected from a group consisting of copper, aluminum, silver, gold, alloys thereof, and combinations thereof.