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Structure and method of semiconductor via testing

  • US 6,498,384 B1
  • Filed: 12/05/2000
  • Issued: 12/24/2002
  • Est. Priority Date: 12/05/2000
  • Status: Expired due to Fees
First Claim
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1. A semiconductor wafer having a via test structure comprising:

  • a semiconductor substrate having a plurality of semiconductor devices;

    a first dielectric layer over the semiconductor substrate having a plurality of openings provided therein;

    first barrier layers lining the openings;

    first conductor cores filling the openings to form second and fourth channels unconnected to the plurality of semiconductor devices;

    a via dielectric layer formed over the dielectric layer and having first and second via openings and third and fourth via openings provided therein respectively open to opposite ends of the second channel and the fourth channel;

    a second dielectric layer formed over the via dielectric layer and having first, third, and fifth channel openings provided therein respectively open to the first via opening, the second and third via openings, and the fourth via opening;

    second barrier layers lining the first, second, third, and fourth via openings and the first, third, and fifth channel openings; and

    second conductor cores filling the first, second, third, and fourth via openings and the first, third and fifth channel openings to form first, third, and fifth channels having the first channel, the first via, the second channel, the second via, the third channel, the third via, the fourth channel, the fourth via, and the fifth channel connected in series whereby the first and fifth channels are probed to determine the presence or absence of voids in the vias.

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