Cancellation of slope compensation effect on current limit

• US 6,498,466 B1
• Filed: 05/23/2000
• Issued: 12/24/2002
• Est. Priority Date: 05/23/2000
• Status: Expired due to Term

• Current Assignee: Analog Devices International Unlimited Company (Analog Devices, Inc.)
• Original Assignee: Linear Technology Corporation (Analog Devices, Inc.)
• Inventors: Edwards, Karl
• Primary Examiner(s): Patel, Rajnikant B.
• Application Number:
  US09/576,517
• Time in Patent Office: 945 Days
• Field of Search: 323/282, 323/283, 323/284, 323/285, 323/286, 323/288, 323/290, 363/26, 363/56, 363/74, 363/78
• US Class Current: 323/282
• CPC Class Codes: G05F 1/573 with overcurrent detector
• CPC Class Codes: H02M 3/33507 with automatic control of the output voltage or current, e.g. flyback converters H02M3/33561, H02M3/33569 take precedence

Abstract

A current-mode switching regulator that maintains a substantially constant maximum current limit over a virtually full range of duty cycles is provided. The regulator has a control circuit that includes a buffer circuit, an adjustable voltage clamp circuit, and a slope compensation circuit. The buffer circuit isolates a control signal from capacitive loading associated with control circuit. The threshold level of the adjustable voltage clamp circuit varies with respect to the amount of slope compensation provided to the voltage regulator. This allows a control voltage to increase as slope compensation increases so that a substantially constant maximum current limit is maintained.

Claims

1. A method for maintaining a maximum output current limit of a current-mode switching regulator;

the method comprising;

generating a slope compensation signal when a duty cycle of the regulator is above a preset value; and

adjusting a current limit point of the regulator as a function of the slope compensation signal to maintain the maximum output current limit of the regulator substantially constant.

2. The method of claim 1 wherein the adjusting further comprises varying a maximum allowable value of a control signal with respect to the slope compensation signal.

3. The method of claim 2 wherein the adjusting further comprises increasing the maximum allowable control signal value as a magnitude of the slope compensation signal increases.

4. The method of claim 2 wherein the adjusting further comprises decreasing the maximum allowable control signal value as a magnitude of the slope compensation signal decreases.

5. The method of claim 4 wherein the adjusting further comprises maintaining the maximum allowable control signal value at a predetermined minimum when the magnitude of the slope compensation signal decreases below a preset value.

6. The method of claim 1 wherein the adjusting further comprises varying a threshold of a voltage clamp circuit with respect to said slope compensation signal.

7. The method of claim 6 wherein the adjusting further comprises increasing the clamp threshold as a magnitude of the slope compensation signal increases.

8. The method of claim 6 wherein the adjusting further comprises decreasing the clamp threshold as a magnitude of the slope compensation signal decreases.

9. The method of claim 8 wherein the adjusting further comprises maintaining the clamp threshold at a predetermined minimum when the magnitude of the slope compensation signal decreases below a preset minimum value.

10. The method of claim 1 wherein said preset value is characterized by a value between about 1% and about 50%.

11. The method of claim 10 wherein the adjusting further comprises producing an error amplifier output signal that is indicative of the difference between a feedback signal and a reference voltage.

12. The method of claim 11 wherein the adjusting further comprises producing a control signal from the error amplifier output signal by substantially isolating the error amplifier output signal from the effects of capacitive loading associated with the error amplifier output signal.

13. The method of claim 12 wherein the adjusting further comprises varying a maximum allowable value of the control signal with respect to the slope compensation signal.

14. The method of claim 1 wherein the generating further comprises creating the slope compensation signal with a switch timing circuit.

15. A method for maintaining a maximum output current limit of a current-mode switching regulator;

the method comprising;

generating a first slope compensation signal when a duty cycle of the regulator is above a preset value;

generating a second slope compensation signal when the duty cycle of the regulator is above the preset value; and

adjusting a current limit point of the regulator as a function of said second slope compensation signal to maintain the current limit substantially constant.

16. The method of claim 15 wherein the first slope compensation signal is generated such that the first slope compensation signal is substantially proportional to the second slope compensation signal.

17. The method of claim 15 wherein the second slope compensation signal establishes a current threshold point at which a switch circuit switches so that the switching regulator remains stable when the duty cycle is at or above a preset value.

18. The method of claim 15 wherein the first slope compensation signal varies a maximum allowable current threshold of the regulator so that the current supplying capability of the regulator remains substantially constant.

19. The method of claim 18 wherein the adjusting further comprises increasing the maximum allowable current threshold of the regulator as a magnitude of the second slope compensation signal increases.

20. The method of claim 18 wherein the adjusting further comprises decreasing the maximum allowable current threshold of the regulator as a magnitude of the second slope compensation signal decreases.

21. The method of claim 20 wherein the adjusting further comprises maintaining the maximum allowable current threshold of the regulator at a predetermined minimum when the magnitude of the second slope compensation signal decreases below a preset value.

22. A switching regulator circuit that maintains a substantially constant maximum output current limit and provides a regulated voltage to a load, the switching regulator having an output circuit that includes a switch circuit coupled to a power source and an output terminal, the output circuit providing a feedback signal that is indicative of the regulated voltage, the switching regulator comprising:

a control circuit coupled to said output circuit that receives said feedback signal, said control circuit providing a first control signal to said output circuit in response to said feedback signal that controls a turn-off threshold of said switch circuit, said control circuit comprising;

(a) a switch timing circuit that generates a ramp signal;

(b) a slope compensation circuit coupled to said switch timing circuit that generates a first slope compensation signal in response to said ramp signal; and

(c) a voltage clamp circuit that receives said first slope compensation signal, said voltage clamp circuit having a clamp threshold that varies with respect to said first slope compensation signal.

23. The switching regulator circuit of claim 22 wherein said slope compensation circuit generates said first slope compensation signal when a duty cycle of said switch circuit is at or above a preset value.

24. The switching regulator circuit of claim 22 wherein said slope compensation circuit generates a second slope compensation signal substantially proportional to said first slope compensation signal.

25. The switching regulator circuit of claim 24 wherein said second slope compensation signal is coupled to establish a threshold point at which the switch circuit switches so that the regulator remains stable when said duty cycle is above a preset value.

26. The switching regulator circuit of claim 25 wherein said first slope compensation signal is coupled to vary a maximum allowable current threshold of the regulator so that the current supplying capability of the regulator remains substantially constant.

27. The switching regulator circuit of claim 25 wherein said switch timing circuit includes an oscillator circuit.

28. The switching regulator circuit of claim 25 wherein said control circuit further comprises:

a comparator circuit having a first input, a second input, and an output, said first input coupled to a signal that is indicative of a current passing through the switch circuit; and

a transistor having a base coupled to said voltage clamp circuit and an emitter coupled to said second slope compensation signal.

29. The switching regulator circuit of claim 28 wherein said second input of said comparator circuit is coupled to a collector of said transistor.

30. The switching regulator circuit of claim 25 wherein said slope compensation circuit comprises:

a first transistor coupled to said switch timing circuit that receives said ramp signal;

a diode-connected transistor coupled to said first transistor; and

a current mirror circuit coupled between said first transistor and said diode-connected transistor.

31. The switching regulator circuit of claim 30 wherein said current mirror circuit comprises:

a second transistor; and

a third transistor, said second and third transistors having common base, and wherein said second transistor generates said second slope compensation signal substantially proportional to said ramp signal and wherein said third transistor generates said first slope compensation signal substantially proportional to said ramp signal.

32. The switching regulator circuit of claim 22 wherein said voltage clamp circuit comprises:

a circuit that provides a fixed voltage potential;

a first transistor having a base coupled to said first slope compensation signal; and

a first resistor having first and second terminals;

said first terminal coupled to said base and said first slope compensation signal, and said second terminal coupled to said fixed voltage potential.

33. The switching regulator circuit of claim 32 wherein said fixed voltage potential circuit comprises:

first and second diode-connected transistors coupled in series; and

a second resistor having first and second terminals, said first terminal coupled to the second terminal of said first resistor and to said second diode-connected transistor, and said second terminal coupled to ground.

34. The switching regulator circuit of claim 22 wherein said control circuit further comprises:

an error amplifier circuit coupled to said feedback signal and to a reference voltage that produces an output signal indicative of the difference between said feedback voltage and said reference voltage; and

a buffer circuit coupled to said error amplifier that receives said output signal and produces a second control signal in response to said output signal, said buffer circuit substantially isolating said second control signal from the effects of capacitive loading associated with said output signal.

35. The switching regulator circuit of claim 34 wherein said buffer circuit comprises at least one transistor.