Display tile structure using organic light emitting materials

• US 6,498,592 B1
• Filed: 11/10/2000
• Issued: 12/24/2002
• Est. Priority Date: 02/16/1999
• Status: Expired due to Term

• Current Assignee: Kal Ramnarayan, MEC Management, LLC (Three Affiliated Tribes of the Fort Berthold Reservation, North Dakota)
• Original Assignee: Sarnoff Corporation (SRI International, Inc.)
• Inventors: Matthies, Dennis Lee
• Primary Examiner(s): Shalwala, Bipin
• Assistant Examiner(s): Kovalick, Vincent E.
• Application Number:
  US09/709,904
• Time in Patent Office: 774 Days
• Field of Search: 345/1.1, 345/36, 345/55, 345/76, 345/77, 345/84, 345/87, 345/100, 349/73, 349/74, 349/153
• US Class Current: 345/1.1
• CPC Class Codes: G02F 1/13336 Combining plural substrates to produce large-area displays, e.g. tiled displays
• CPC Class Codes: G02F 1/1345 Conductors connecting electrodes to cell terminals
• CPC Class Codes: G02F 2201/42 Arrangements for providing conduction through an insulating substrate
• CPC Class Codes: G09G 2300/026 Video wall, i.e. juxtaposition of a plurality of screens to create a display screen of bigger dimensions
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2310/0278 Details of driving circuits arranged to drive both scan and data electrodes
• CPC Class Codes: G09G 2320/043 Preventing or counteracting the effects of ageing
• CPC Class Codes: G09G 2320/048 using evaluation of the usage time
• CPC Class Codes: G09G 2360/141 the light conveying information used for selecting or modulating the light emitting or modulating element
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/2085 Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination
• CPC Class Codes: G09G 3/2088 with use of a plurality of processors, each processor controlling a number of individual elements of the matrix
• CPC Class Codes: G09G 3/3208 organic, e.g. using organic light-emitting diodes [OLED]
• CPC Class Codes: H01L 25/167 comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H04N 9/12 Picture reproducers H04N9/11 takes precedence
• CPC Class Codes: H04N 9/30 using solid-state colour display devices
• CPC Class Codes: H10K 50/805 : Electrodes
• CPC Class Codes: H10K 50/86 : Arrangements for improving contrast, e.g. preventing reflection of ambient light
• CPC Class Codes: H10K 59/131 : Interconnections, e.g. wiring lines or terminals
• CPC Class Codes: H10K 59/179 : Interconnections, e.g. wiring lines or terminals
• CPC Class Codes: H10K 59/18 : Tiled displays
• CPC Class Codes: H10K 59/805 : Electrodes
• CPC Class Codes: H10K 59/8792 : comprising light absorbing layers, e.g. black layers

Abstract

A tiled display structure is fabricated on a single substrate that also serves as a circuit board containing electronic components. Electrodes are formed on the substrate and the remainder of the display section is formed on the electrodes. The pixel elements use patterned display material, and occupy only a portion of the pixel structure. The electronic components are mounted on the substrate using exceptionally long leads to assist in thermal management of tiles. Alternatively, each tile includes a fin structure on the circuit board surface onto which electronic components are mounted and are not in contact with the substrate. Alternatively, each tile includes a flexible circuit board mounted on the substrate, a portion of which is bent away from the substrate. Electronic components are coupled to this portion of the flexible circuit boards such that the components are not in contact with the substrate to assist in thermal management.

Claims

1. An electronic display structure comprising;

a substrate having a top surface and a bottom surface;

the bottom surface of the substrate being a circuit board onto which circuitry for providing a plurality of electrical signals is coupled;

a picture element (pixel) structure having a predetermined area including;

a first electrode, formed on the top surface of the substrate;

a display material having a bottom surface and a top surface, the bottom surface being in close proximity to the first electrode; and

a second electrode, positioned in close proximity to the top surface of the display material;

a first connecting via extending from the bottom surface of the substrate to couple the first electrode to receive a first electrical signal of the plurality of electrical signals; and

a second connecting via extending from the bottom surface of the substrate and through the pixel structure to couple the second electrode to receive a second electrical signal of the plurality of electrical signals, wherein the first electrode and the display material are sized and arranged such that the second connecting via does not interfere with the first electrode or the display material.

2. The electronic display structure of claim 1, wherein the substrate comprises a ceramic material.

3. The electronic display structure of claim 2, wherein the ceramic material comprises worked alumina.

4. The electronic display structure of claim 1, wherein the substrate comprises a low-temperature co-fired ceramic and metal structure.

5. The electronic display structure of claim 1, wherein the display material comprises materials that form an organic light emitting diode.

6. An electronic display structure comprising;

a substrate having a top surface and a bottom surface;

a plurality of pixel structures, coupled to the top surface of the substrate, arranged in a matrix having rows and columns, and including a plurality of contacts corresponding to the rows and columns of the matrix for receiving electrical signals;

wherein each pixel structure includes a distinct portion of display material physically separated from the display material of any other pixel structure;

pixel driving circuitry coupled to the bottom surface of the substrate and adapted to provide a plurality of electrical signals which activate ones of the plurality of pixel structures in respective rows and columns of the matrix of pixel structures;

a plurality of electrical contacts coupled to receive the plurality of electrical signals provided by the pixel driving circuitry, the plurality of electrical contacts having at least a one-to-one correspondence with the plurality of contacts of the matrix of pixel structures; and

a plurality of vias for coupling the plurality of electrical contacts to the plurality of contacts of the matrix of pixel structures.

7. The electronic display structure of claim 6, further comprising timing circuitry, coupled to the bottom surface of the substrate and responsive to a timing signal to sequentially scan the pixel driving circuitry to provide electrical signals to successive rows of the matrix of pixel structures.

8. The electronic display structure of claim 7, further comprising a memory coupled to the bottom surface of the substrate, the memory storing image data to be provided to the driving circuitry.

9. The electronic display structure of claim 7, further comprising means for coupling at least one element of the pixel driving circuitry and the timing circuitry to the substrate in a manner that tends to avoid hot spots in the substrate.

10. The electronic display structure of claim 9, wherein;

the at least one element is implemented as an integrated circuit (IC); and

the means for coupling comprises a plurality of long leads of the IC electrically coupling the IC to the substrate such that the long leads of the IC are in contact with the substrate to the substantial exclusion of any other part of the IC.

11. The electronic display structure of claim 9, wherein;

the means for coupling the at least one element comprises a heat fin structure coupled to the bottom surface of the substrate which couples the at least one element to the substrate such that the at least one element is not in contact with substrate.

12. The electronic display structure of claim 9, wherein;

the means for coupling the at least one element comprises a flexible circuit board coupled to the bottom surface of the substrate and formed so that a portion of the flexible circuit board extends away from the bottom surface of the substrate; and

means for coupling the at least one element to the portion of the flexible circuit board such that the at least one element is not in contact with substrate.

13. The electronic display structure of claim 6, wherein the distinct portion of display material comprises a distinct portion of organic materials that form a light emitting diode.

14. A tiled display structure comprising a plurality of image tiles, each tile comprising;

a substrate having a top surface and a bottom surface;

a plurality of pixel structures, coupled to the top surface of the substrate, arranged in a matrix having rows and columns and including a plurality of contacts for receiving electrical signals;

wherein each pixel structure includes a distinct portion of display material physically separated from the display material of any other pixel structure;

pixel driving circuitry coupled to the bottom surface of the substrate and adapted to provide a plurality of electrical signals which are conditioned to activate respective ones of the plurality of pixel structures;

a plurality of electrical contacts coupled to receive the plurality of electrical signals provided by the pixel driving circuitry, the plurality of electrical contacts having at least a one-to-one correspondence with the plurality of contacts of the matrix of pixel structures; and

a plurality of vias for coupling the plurality of electrical contacts to the plurality of contacts of the matrix of pixel structures;

a rigid back panel and frame structure including a plurality of spring elements which hold the plurality of image tiles in position to form the tiled display structure; and

a plurality of flexible connections which provide operational power to the plurality of image tiles.

15. The electronic display structure of claim 14, further comprising auxiliary circuitry including at least one of;

a memory coupled to the bottom surface of the substrate, the memory storing image data to be provided to the driving circuitry; and

timing circuitry, coupled to the bottom surface of the substrate and responsive to a timing signal to sequentially scan the pixel driving circuitry to provide electrical signals to successive rows of the matrix of pixel structures.

16. The electronic display structure of claim 14, wherein the distinct portion of display material comprises a distinct portion of organic light emitting diode material.

17. A tiled display structure comprising a plurality of image tiles, each tile comprising;

a substrate having a top surface and a bottom surface;

a display section coupled to the top surface of the substrate, including a glass substrate and a plurality of pixel structures, each pixel structure defining a pixel area and having an active region which occupies a portion of the pixel area, the plurality of pixel structures being arranged in a matrix having rows and columns and including a plurality of contacts for receiving electrical signals;

pixel driving circuitry coupled to the bottom surface of the substrate and adapted to provide a plurality of electrical signals to respective ones of the electrical contacts of the pixel structures to selectively activate the plurality of pixel structures;

a transparent front panel having a plurality of rows and columns of dark-colored lines, the plurality of lines being substantially equal in width and defining transparent regions on the front panel for pixel positions in the tiled display device; and

means for securing the glass substrate of the display sections of the plurality of tiles to the transparent front panel to align the active region of each pixel area on each tile with a respectively different one of the defined transparent regions on the front panel.

18. A tiled display structure comprising a plurality of image tiles, each tile comprising;

a substrate having a top surface and a bottom surface;

a display section coupled to the top surface of the substrate, including a glass substrate having a front surface and a back surface, the display section further including a plurality of pixel structures, coupled to the back surface of the glass substrate, each pixel structure defining a pixel area and having an active region which occupies a portion of the pixel area, the plurality of pixel structures being arranged in a matrix having rows and columns and including a plurality of contacts for receiving electrical signals, wherein the front surface of the glass substrate includes a plurality of dark-colored lines having a predetermined width which form a black matrix surrounding the active regions of the plurality of pixel structures; and

pixel driving circuit coupled to the bottom surface of the substrate and adapted to provide a plurality of electrical signals to respective ones of the electrical contacts of the pixel structures to selectively activate the plurality of pixel structures.

19. The tiled display structure of claim 18, further comprising a plurality of mullions each of which joins the glass substrate of one of the image tiles to the glass substrate of another one of the image tiles, the mullions having a “

T”

shaped cross section which defines a crossbar and a stem, the crossbar having a width substantially equal to the predetermined width, wherein the plurality of mullions join the plurality of tiles to form the tiled display structure.

20. A method of constructing an electronic display structure on a substrate having a top surface and a bottom surface comprising the steps of;

forming a plurality of vias extending from the bottom surface of the substrate to the top surface of the substrate;

forming a circuit board structure on the bottom surface of the substrate, the circuit board structure including a plurality of electrical contacts coupled to the plurality of vias;

mounting pixel driving circuitry on the circuit board structure and coupling the driving circuitry to the plurality of vias to provide a plurality of electrical signals;

forming a plurality of row electrodes on the top surface of the substrate;

coupling each row electrode of the plurality of row electrodes to at least one of the vias to receive a respective row electrical signal of the plurality of electrical signals;

forming a plurality of pixel regions each containing at least one distinct active pixel area, each distinct active pixel area composed of at least one layer of display material, wherein at least one of the distinct active pixel areas is on top of each row electrode;

forming a plurality of transparent column electrodes over the distinct active pixel areas, wherein each distinct active pixel area is coupled to one transparent column electrode of the plurality of transparent column electrodes; and

coupling each transparent column electrode of the plurality of transparent column electrodes to at least one of the vias to receive a respective column electrical sign of the plurality of electrical signals.

21. The method of claim 20, wherein the plurality of row electrodes and the plurality of active pixel areas are sized and arranged such that the at least one via coupled to the at least one transparent column electrode of the plurality of transparent column electrodes does not interfere with the plurality of row electrodes or the plurality of distinct active pixel areas.

22. The method of claim 20, wherein the substrate comprises alumina.

23. The method of claim 22, wherein the step of forming a plurality of vias extending from the bottom surface of the substrate to the top surface of the substrate comprises the steps of;

coating the top surface of the alumina substrate with a planarization layer;

working a plurality of holes in the coated alumina substrate extending from the bottom surface of coated alumina substrate through the planarization layer; and

forming a conductor in each of the plurality of holes coupled to the bottom surface of the coated substrate and the planarization layer.

24. The method of claim 23, wherein the planarization layer comprises spin-on-glass.

25. The method of claim 20, wherein the substrate is comprised of a low-temperature co-fired ceramic and metal structure.

26. The method of claim 20, wherein the plurality of pixel regions are of substantially equal size and arranged in a matrix having a plurality of rows and a plurality of columns such that the matrix covers substantially all of the top surface of the substrate.

27. A method of constricting a electronic display tile including a substrate having a top surface, a bottom surface, a pair of horizontal edges, and a pair of vertical edges, the top surface of each substrate being covered by a plurality of pixel regions arranged in a matrix of rows and columns, comprising the steps of;

forming a plurality of vias extending from the bottom surface of the substrate to the top surface of the substrate;

forming a circuit board structure on the bottom surface of the substrate, the circuit board structure including a plurality of electrical contacts coupled to the plurality of vias;

forming a plurality of row electrodes on the top surface of the substrate;

coupling each row electrode of the plurality of row electrodes to at least one of the vias to receive a respective row electrical signal of the plurality of electrical signals;

forming at least one distinct active pixel area in each of the plurality of pixel regions, wherein the distinct active pixel area includes at least one layer of display material and is coupled to one row electrode of the plurality of row electrodes;

forming a plurality of transparent column electrodes over the plurality of distinct active pixel areas, wherein each distinct active pixel area is coupled to one transparent column electrode of the plurality of transparent column electrodes; and

coupling each transparent column electrode of the plurality of transparent column electrodes to at least one of the vias to receive a respective column electrical signal of the plurality of electrical signals.

28. The method of claim 27, wherein the plurality of row electrodes and the plurality of distinct active pixel areas are sized and arranged such that the at least one via coupled to the plurality of transparent column electrodes does not interfere with the plurality of row electrodes or the plurality of distinct active pixel areas.

29. The method of claim 27, wherein the top surface of each substrate is substantially completely covered by the plurality of pixel regions.

30. The method of claim 29, further comprising the step of;

machining the pair of horizontal edges of the substrate with a pair of complementary horizontal edge patterns arranged such that the pair of complimentary horizontal edge patterns do not interfere with the plurality of distinct active pixel areas;

whereby adjacent tiles in a tiled display system may be precisely aligned horizontally.

31. The method of claim 29, further comprising the step of;

machining the pair of vertical edges of the substrate with a pair of complementary vertical edge patterns arranged such that the pair of complimentary vertical edge patterns do not interfere with the plurality of distinct active pixel areas;

whereby adjacent tiles in a tiled display system may be precisely aligned vertically.

32. The method of claim 27, wherein the at least one layer of display material comprises at least one layer of an organic light emitting diode material.

33. A tiled display structure comprising a plurality of image tiles, each tile comprising;

a glass substrate having a front surface and a back surface;

a display section coupled to the back surface of the glass substrate, including a plurality of pixel structures, each pixel structure defining a pixel area and having an active region which occupies a portion of the pixel area, the plurality of pixel structures being arranged in a matrix having rows and columns and including a plurality of contacts for receiving electrical signals;

a passivation layer which covers each pixel structure in the display section and does not cover the plurality of contacts; and

pixel driving circuitry coupled to the back surface of the glass substrate and arranged so as not to interfere with the active regions of the pixel structures, the pixel driving circuitry adapted to provide a plurality of electrical signals to respective ones of the electrical contacts of the pixel structures to selectively activate the plurality of pixel structures.

34. The tiled display structure of claim 33, further comprising a plurality of dark-colored lines coupled to the front surface of the glass substrate forming a black matrix surrounding the active regions of the plurality of pixel structures, each line having a predetermined width, the predetermined width being less than a maximum width at wich a substantial amount of light from the plurality of pixel structures is blocked by the plurality of dark-colored lines and greater than a minimum width at which the pixel driving circuitry is substantially visible through the front surface of the glass substrate.

35. The tiled display structure of claim 33, further comprising a plurality of dark-colored lines coupled to the back surface of the glass substrate forming a black matrix surrounding the active regions of the plurality of pixel structures, the plurality of dark-colored lines disposed between the glass substrate and the pixel driving circuitry.

36. The tiled display structure of claim 33, wherein the passivation layer is disposed between the display section and the pixel driving circuitry.

37. The tiled display structure of claim 36, wherein the passivation layer is formed of a dark-colored material and extends over substantially all of the back surface of the glass substrate.

38. The tiled display structure of claim 33, wherein the pixel driving circuitry is coupled to the back surface of the glass substrate by at least one of;

a plurality of solder bumps;

a plurality of flip chip connectors;

a plurality of long leads in contact with the display section to the substantial exclusion of any other part Of the pixel driving circuitry.

39. The tiled display structure of claim 33, wherein;

the portion of each pixel area occupied by the corresponding active region is less than one half of the pixel area; and

each pixel area adjacent to the at least one edge has a pixel area that is less than the pixel area of a pixel that is distant from the edge.

40. A tiled display structure having a plurality of display tiles comprising;

a substrate having at least one edge; and

a plurality of active pixel areas, each pixel area including a discrete portion of display material, the active pixel areas being arranged on the substrate in a matrix of rows and columns, each active pixel area substantially isolated, electrically and optically, from remaining active pixel areas and physically separated from an adjacent active pixel area by a determined distance;

wherein active pixel areas nearest to the at least one edge have a separation from the at least one edge that is less than the predetermined distance;

whereby, when the plurality of image tiles are fit together, the active pixel areas nearest to the at least one edge of one image tile are separated from an adjacent active pixel area of an adjacent image tile by the predetermined distance.

41. The tiled display structure of claim 40, wherein the plurality of active pixel areas include a plurality of sub-pixels.