Applications for non-volatile memory cells

• US 6,498,739 B2
• Filed: 10/01/2001
• Issued: 12/24/2002
• Est. Priority Date: 02/26/1999
• Status: Expired due to Fees

• Current Assignee: L&H Applications USA, Inc
• Original Assignee: Micron Technology, Inc.
• Inventors: Noble, Wendell P., Cloud, Eugene H.
• Primary Examiner(s): Ho, Hoai
• Assistant Examiner(s): Auduong, Gene N.
• Application Number:
  US09/968,643
• Publication Number:
  US 20020015322A1
• Time in Patent Office: 449 Days
• Field of Search: 365/51, 365/63, 438/241, 438/258, 438/253-256, 438/396-399, 257/306-311
• US Class Current: 365/51
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 16/02 electrically programmable
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Applications and methods for DRAM technology compatible non-volatile memory cells are presented. An example illustrating the applications and methods includes a circuit switch. The circuit switch has a non-volatile memory cell which a metal oxide semiconductor field effect transistor (MOSFET) formed in a semiconductor substrate, a capacitor, and a vertical electrical via coupling a bottom plate of the capacitor through an insulator layer to a gate of MOSFET. A wordline is coupled to a top plate of the capacitor in the non-volatile memory cell. A sourceline is coupled to a source region of the MOSFET in the non-volatile memory cell. A bit line is coupled to a drain region of the MOSFET in the non-volatile memory cell and coupled to a logic/select circuit.

Claims

1. A method of forming a circuit switch, comprising:

forming a non-volatile memory cell, wherein forming the non-volatile memory cell includes;

forming a metal oxide semiconductor field effect transistor (MOSFET) in a semiconductor substrate;

forming a stacked capacitor according to a dynamic random access memory (DRAM) process flow; and

forming a vertical electrical via, wherein forming the vertical electrical via includes coupling a bottom plate of the stacked capacitor through an insulator layer to a gate of MOSFET;

forming a wordline coupled to a top plate of the stacked capacitor in the non-volatile memory cell;

forming a sourceline coupled to a source region of the MOSFET in the non-volatile memory cell; and

forming a bit line coupled to a drain region of the MOSFET in the non-volatile memory cell and coupled to a logic/select circuit.

2. The method of claim 1, wherein forming the stacked capacitor includes forming the bottom plate of the stacked capacitor in a cup shape having interior walls and exterior walls and is separated by a capacitor dielectric from the top plate.

3. The method of claim 1, wherein forming the capacitor dielectric includes forming the capacitor dielectric conformal to the bottom plate, and forming the top plate conformal to the capacitor dielectric, a portion of the top plate being located within the interior walls of the bottom plate.

4. The method of claim 1, wherein forming the non-volatile memory cell includes forming an EEPROM cell.

5. The method of claim 1, wherein forming the logic/select circuit includes coupling the logic/select circuit to a multiplexor, and coupling a first circuit line and second circuit line to the multiplexor such that the multiplexor couples the first circuit line to the second circuit line when the non-volatile memory cell is in a first programmed state, and such that the multiplexor decouples the first circuit line from the second circuit line when the non-volatile memory cell is in a second programmed state.

6. The method of claim 5, wherein coupling the second circuit line to the multiplexor includes coupling a redundant DRAM wordline to the multiplexor.

7. A method for forming a circuit switch array, comprising:

forming a number of non-volatile memory cells, wherein forming each non-volatile memory cell includes;

forming a metal oxide semiconductor field effect transistor (MOSFET) in a semiconductor substrate;

forming a stacked capacitor according to a dynamic random access memory (DRAM) process in a subsequent layer above the MOSFET and separated from the MOSFET by an insulator layer; and

forming an electrical contact, wherein forming the electrical contact includes coupling a bottom plate of the stacked capacitor through the insulator layer to the gate of MOSFET;

coupling a control line to a top plate of the stacked capacitor in the number of non-volatile memory cells;

coupling a sourceline to a source region of the MOSFET in the number of non-volatile memory cells; and

coupling a bit line to a drain region of the MOSFET in the number of non-volatile memory cells and coupling the bit line to a multiplexor which couples a number of input circuit lines to a number of output circuit lines.

8. The method of claim 7, wherein coupling the bit line to a multiplexor includes coupling the bit line to a logic/select circuit and coupling the logic/select to the multiplexor.

9. The method of claim 7, wherein the method further includes coupling a number of redundant output circuit lines to the multiplexor.

10. A method for forming a circuit repair array, comprising:

forming a number of non-volatile memory cells on a dynamic random access memory (DRAM) chip, wherein forming each non-volatile memory cell includes;

forming a metal oxide semiconductor field effect transistor (MOSFET) in a semiconductor substrate;

forming a stacked capacitor according to a DRAM process in a subsequent layer above the MOSFET and separated from the MOSFET by an insulator layer, wherein a bottom plate of the stacked capacitor is cup shaped having interior walls and exterior walls and is separated by a capacitor dielectric from a top plate;

forming an electrical contact, wherein forming the electrical contact includes coupling the bottom plate of the stacked capacitor through the insulator layer to the gate of MOSFET;

coupling a control line to the top plate of the stacked capacitor in the number of non-volatile memory cells;

coupling a sourceline to a source region of the MOSFET in the number of non-volatile memory cells; and

coupling a bit line to a drain region of the MOSFET in the number of non-volatile memory cells and coupling the bit line to a multiplexor which couples a number of input circuit lines to a number of output circuit lines.

11. The method of claim 10, wherein forming the stacked capacitor includes forming a capacitor dielectric conformal to the bottom plate, and forming the top plate conformal to the capacitor dielectric, a portion of the top plate being located within the interior walls of the bottom plate.

12. The method of claim 10, wherein forming each non-volatile memory cell includes forming an EEPROM cell.

13. The method of claim 10, wherein coupling the bit line to the multiplexor includes coupling a bit line to a logic/select circuit and coupling the logic/select circuit to a multiplexor.

14. The method of claim 10, wherein the method further includes coupling a number of redundant output circuit lines to the multiplexor.

15. A method for forming an electronic system, comprising:

forming a processor;

coupling a system bus to the processor;

forming a dynamic random access memory (DRAM) chip coupled to the system bus;

forming a circuit switch on the DRAM chip including;

forming a non-volatile memory cell, wherein forming the non-volatile memory cell includes;

forming a metal oxide semiconductor field effect transistor (MOSFET) in a semiconductor substrate;

forming a stacked capacitor according to a DRAM process in a subsequent layer above the MOSFET and separated from the MOSFET by an insulator layer, wherein a bottom plate of the stacked capacitor is cup shaped having interior walls and exterior walls and is separated by a capacitor dielectric from a top plate;

forming a vertical electrical via, wherein forming the vertical electrical via includes coupling the bottom plate of the stacked capacitor through an insulator layer to a gate of MOSFET;

forming a wordline coupled to the top plate of the stacked capacitor in the non-volatile memory cell;

forming a sourceline coupled to a source region of the MOSFET in the non-volatile memory cell; and

forming a bit line coupled to a drain region of the MOSFET in the non-volatile memory cell and coupled to a logic/select circuit.

16. The method of claim 15, wherein forming the stacked capacitor includes forming a capacitor dielectric conformal to the bottom plate, and forming the top plate conformal to the capacitor dielectric, a portion of the top plate being located within the interior walls of the bottom plate.

17. The method of claim 15, wherein forming the non-volatile memory cell includes forming an EEPROM cell.

18. The method of claim 15, wherein forming the bit line coupled to the logic/select circuit includes coupling the logic/select circuit to a multiplexor, and coupling a first circuit line and second circuit line to the multiplexor such that the multiplexor couples the first circuit line to the second circuit line when the non-volatile memory cell is in a first programmed state, and such that the multiplexor decouples the first circuit line from the second circuit line when the non-volatile memory cell is in a second programmed state.

19. The method of claim 18, wherein coupling the second circuit line to the multiplexor includes coupling a redundant DRAM wordline to the multiplexor.

20. A method for forming a shadow random access memory (RAM) cell, comprising:

forming a non-volatile memory cell, wherein forming the non-volatile memory cell includes;

forming a first metal oxide semiconductor field effect transistor (MOSFET) in a semiconductor substrate;

forming a stacked capacitor according to a DRAM process in a subsequent layer above the first MOSFET and separated from the first MOSFET by an insulator layer, wherein a bottom plate of the stacked capacitor is cup shaped having interior walls and exterior walls and is separated by a capacitor dielectric from a top plate;

forming a vertical electrical via which couples the bottom plate of the stacked capacitor through an insulator layer to a gate of the first MOSFET; and

forming a dynamic random access memory (DRAM) cell including a second MOSFET and a second capacitor, wherein forming the DRAM cell includes forming a first diffused region which is shared between the first MOSFET and the second MOSFET.

21. The method of claim 20, wherein forming the stacked capacitor includes forming a capacitor dielectric conformal to the bottom plate, and forming the top plate conformal to the capacitor dielectric, a portion of the top plate being located within the interior walls of the bottom plate.

22. The method of claim 20, wherein forming the non-volatile memory cell includes forming an electronically erasable and programmable read only memory (EEPROM) cell.

23. The method of claim 20, wherein forming the first MOSFET includes forming an n-channel metal oxide semiconductor (NMOS) transistor.

24. A method for forming an array of shadow random access memory (RAM) cells, comprising:

forming a number of non-volatile memory cells, wherein forming each non-volatile memory cell includes;

forming a first metal oxide semiconductor field effect transistor (MOSFET) in a semiconductor substrate;

forming a stacked capacitor according to a dynamic random access memory (DRAM) process in a subsequent layer above the first MOSFET and separated from the first MOSFET by an insulator layer, wherein a bottom plate of the stacked capacitor is cup shaped having interior walls and exterior walls and is separated by a capacitor dielectric from a top plate;

coupling an electrical contact between the bottom plate of the stacked capacitor through the insulator layer to the gate of the first MOSFET;

forming a number of DRAM cells, wherein each DRAM cell includes a second MOSFET and a second capacitor coupled to a first diffused region for the second MOSFET, and wherein the first diffused region is shared between the first MOSFET and the second MOSFET;

forming a control line coupled to the top plate of the stacked capacitor in the number of non-volatile memory cells;

forming a first group of bit lines coupled to a second diffused region of the first MOSFET in the number of non-volatile memory cells; and

forming a second group of bit lines coupled to a second diffused region of the second MOSFET in the number of DRAM cells.

25. The method of claim 24, wherein forming a number of DRAM cells includes forming a second stacked capacitor coupled to a first diffused region for the second MOSFET.

26. The method of claim 24, wherein forming the stacked capacitor includes forming a capacitor dielectric conformal to the bottom plate, and forming the top plate conformal to the capacitor dielectric, a portion of the top plate being located within the interior walls of the bottom plate.

27. The method of claim 24, wherein forming each non-volatile memory cell includes forming an electronically erasable and programmable read only memory (EEPROM) cell.

28. The method of claim 24, wherein forming the array of shadow RAM cells includes forming a serial numbering device.

29. A method for forming an electronic system, comprising:

forming a processor;

coupling a system bus to the processor;

forming a dynamic random access memory (DRAM) chip coupled to the system bus;

forming a number of non-volatile memory cells on the DRAM chip, wherein forming each non-volatile memory cell includes;

forming a first metal oxide semiconductor field effect transistor (MOSFET) in a semiconductor substrate;

forming a stacked capacitor according to a dynamic random access memory (DRAM) process in a subsequent layer above the first MOSFET and separated from the first MOSFET by an insulator layer, wherein a bottom plate of the stacked capacitor is cup shaped having interior walls and exterior walls and is separated by a capacitor dielectric from a top plate;

coupling an electrical contact between the bottom plate of the stacked capacitor through the insulator layer to the gate of the first MOSFET;

forming a number of DRAM cells on the DRAM chip, wherein each DRAM cell includes a second MOSFET and a second capacitor coupled to a first diffused region for the second MOSFET, and wherein the first diffused region is shared between the first MOSFET and the second MOSFET;

forming a control line coupled to the top plate of the stacked capacitor in the number of non-volatile memory cells;

forming a first group of bit lines coupled to a second diffused region of the first MOSFET in the number of non-volatile memory cells; and

forming a second group of bit lines coupled to a second diffused region of the second MOSFET in the number of DRAM cells.

30. The method of claim 29, wherein forming a number of DRAM cells includes forming a second stacked capacitor coupled to a first diffused region for the second MOSFET.

31. The method of claim 29, wherein forming the stacked capacitor includes forming a capacitor dielectric conformal to the bottom plate, and forming the top plate conformal to the capacitor dielectric, a portion of the top plate being located within the interior walls of the bottom plate.

32. The method of claim 29, wherein forming each non-volatile memory cell includes forming an electronically erasable and programmable read only memory (EEPROM) cell.

33. The method of claim 29, wherein forming the array of shadow RAM cells includes forming a serial beginning input/output system (BIOS).