Semiconductor memory device

• US 6,498,741 B2
• Filed: 12/21/2000
• Issued: 12/24/2002
• Est. Priority Date: 12/22/1998
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Hara, Takahiko, Koyanagi, Masaru, Hisada, Toshiki, Kushiyama, Natsuki, Matsudera, Katsuki, Yoneya, Kazuhide, Nakagawa, Kaoru
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): NGUYEN, HIEN N
• Application Number:
  US09/746,890
• Publication Number:
  US 20010000990A1
• Time in Patent Office: 733 Days
• Field of Search: 365/63, 365/51, 365/189.05, 365/230.06, 365/230.08, 365/230.03, 365/189.12
• US Class Current: 365/63
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay

Abstract

A semiconductor memory device is provided which ensures the symmetry of memory data transmission time and a high-speed operation and has large write/read operation margin with no need of increasing the chip area. By placing a horizontally long peripheral circuit section in the middle in the vertical direction of a semiconductor chip, placing a vertically long shift register section above and below and perpendicularly to the peripheral circuit section, and making the memory core and shift register arrangement symmetrical in the horizontal direction, the data/signal lines between the memory core and the shift register section can be made short and the symmetry of the interconnections can be maintained, which allows the implementation of a high-speed and large-margin semiconductor memory device. In addition, a faster semiconductor memory can be obtained by forming the shift register section by stacking shift registers each corresponding to a data block and selecting the order in which the shift registers are stacked so that the length of interconnections between the peripheral circuit and the shift register is minimized.

Claims

1. A semiconductor memory device comprising:

a peripheral circuit section including a plurality of I/O circuits;

a shift register section placed so that its longitudinal line is perpendicular to the longitudinal line of the peripheral circuit section; and

a memory core section including a memory cell array and placed adjacent to the shift register section along the longitudinal line of the shift register section.

2. The semiconductor memory device according to claim 1, wherein the memory core section and the shift register section are placed on the chip symmetrically with respect to the center line of the semiconductor chip.

3. The semiconductor memory device according to claim 1, wherein the memory core section is placed adjacent to one side of the shift register section along its longitudinal line.

4. The semiconductor memory device according to claim 1, wherein the memory core section is placed adjacent to both sides of the shift register section along its longitudinal line.

5. The semiconductor memory device according to claim 1, wherein the memory core section comprises first and second memory cores placed adjacent to both sides of the shift register section and the shift register section comprises a first shift register which operates in association with the first memory core and a second shift register which operates in association with the second memory core.

6. The semiconductor memory device according to claim 1, wherein the memory core section comprises first and second memory cores placed adjacent to both sides of the shift register section and the shift register section operates in association with the first and second memory cores.

14. The semiconductor memory device according to claim 1, wherein a fuse circuit and a DQ buffer arc placed adjacent to a side of the shift register section along its longitudinal line.

15. The semiconductor memory device according to claim 1, wherein a plurality of pads are placed along a line oriented parallel to the longitudinal line of the peripheral circuit section.

7. A semiconductor memory device comprising:

a peripheral circuit section including a plurality of I/O circuits;

a shift register section placed so that its longitudinal line is perpendicular to the longitudinal line of the peripheral circuit section;

a memory core section including a memory cell array and placed adjacent to the shift register section along the longitudinal line of the shift register section; and

the shift register section including a plurality of shift registers which are arranged along the vertical side of the chip and correspond one for one with the plurality of I/O circuits.

20. The semiconductor memory device according to claim 7, wherein a plurality of pads are placed along a line oriented parallel to the longitudinal line of the peripheral circuit section.

8. A semiconductor memory device comprising:

a peripheral circuit section including a plurality of I/O circuits;

a shift register section placed so that its longitudinal line is perpendicular to the longitudinal line of the peripheral circuit section;

a memory core section including a memory cell array and placed adjacent to the shift register section along the longitudinal line of the shift register section; and

the shift register section including a plurality of shift registers which are arranged along the vertical direction of the chip and correspond one for one with bits of write/read serial data.

9. The semiconductor memory device according to claim 8, wherein the shift register section comprises a first shift register section having a plurality of shift registers which correspond one for one with even bits of the serial data and a second shift register section having a plurality of shift registers which correspond one for one with odd bits of the serial data, the first and second shift register sections being arranged independently.

10. The semiconductor memory device according to claim 8, wherein write/read data is transferred in one of the following transfer modes:

a transfer mode in which, at data write time, serial data is transferred from a shift register which is close to the shift register section to a shift register which is far from the peripheral circuit section;

a transfer mode in which, at data read time, parallel data read from the memory core section is transferred to a shift register close to the peripheral circuit section;

a transfer mode in which, at data write time, serial data is transferred from a shift register close to the peripheral circuit section to a shift register far from the peripheral circuit section and then turns back toward a shift register close to the peripheral circuit section; and

a transfer mode in which, at data read time, parallel data read from the memory core section is transferred to a shift register far from the peripheral circuit section and then turns back toward a shift register close to the peripheral circuit section.

11. The semiconductor memory device according to claim 8, wherein a write register forming a part of the shift register section is arranged such that a latch control signal for a plurality of latch circuits is transferred in synchronization with an internal clock signal, bits of serial write register entered into the write register are taken into the latch circuits in a given order, and the bits of the write data are taken from the latch circuits in parallel, and, in the write data transfer mode of the shift register section, by a latch control signal entered into a shift register in the shift register section which is close to the peripheral circuit section being transferred toward a shift register far from the peripheral circuit section, bits of serial write data entered into a shift register close to the peripheral circuit section are sequentially taken into latch circuits in the shift registers from close to the peripheral circuit section to far from the peripheral circuit section.

12. The semiconductor memory device according to claim 9, wherein write/read data is transferred in one of the following transfer modes:

a transfer mode in which, at data write time, serial data is transferred from a shift register close to the shift register section to a shift register far from the peripheral circuit section;

a transfer mode in which, at data read time, parallel data read from the memory core section is transferred to a shift register close to the peripheral circuit section;

a transfer mode in which, at data write time, serial data is transferred from a shift register close to the peripheral circuit section to a shift register fir from the peripheral circuit section and then turns back toward a shift register close to the peripheral circuit section; and

a transfer mode in which, at data read time, parallel data read from the memory core section is transferred to a shift register far from the peripheral circuit section and then turns back toward a shift register close to the peripheral circuit section.

13. The semiconductor memory device according to claim 9, wherein a write register forming a part of the shift register section is arranged such that a latch control signal for a plurality of latch circuits is transferred in synchronization with an internal clock signal, bits of serial write register entered into the write register are taken into the latch circuits in a given order, and the bits of the write data are taken from the latch circuits in parallel, and, in the write data transfer mode of the shift register section, by a latch control signal entered into a shift register in the shift register section which is close to the peripheral circuit section being transferred toward a shift register far from the peripheral circuit section, bits of serial write data entered into a shift register close to the peripheral circuit section are sequentially taken into latch circuits in the shift registers from close to the peripheral circuit section to far from the peripheral circuit section.

16. A semiconductor memory device comprising

a peripheral circuit section including a plurality of I/O circuits;

four shift register sections comprised of a first shift register section, a second shift register section, a third shift register section and a fourth shift register section; and

a memory core section including a memory cell array and placed adjacent to both sides of each of the first to the fourth shift register sections along its longitudinal line;

wherein each of the first to the fourth shift register sections has a longitudinal line perpendicular to the longitudinal line of the peripheral circuit section, and the first and second shift register sections are placed to one side of the peripheral circuit section along its longitudinal line and the third and fourth shift register sections are placed to the other side of the peripheral circuit section along its longitudinal line.

17. A semiconductor memory device according to claim 16, wherein

the first and third shift resistor section are placed in such a manner that they are symmetric with respect to the longitudinal line of the peripheral circuit section,

the second and fourth shift resistor sections are placed in such a manner that they are symmetric with respect to the longitudinal line of the peripheral circuit section.

18. A semiconductor memory device according to claim 16, wherein a DQ buffer is placed adjacent to a side of each of the first to the fourth shift register sections along its longitudinal line.

19. The semiconductor memory device according to claim 16, wherein a plurality of pads are placed along a line oriented parallel to the longitudinal line of the peripheral circuit section.