Memory array organization for static arrays

• US 6,498,754 B2
• Filed: 02/15/2001
• Issued: 12/24/2002
• Est. Priority Date: 02/15/2001
• Status: Expired due to Term

• Current Assignee: ARRIS Enterprises LLC (CommScope Holding Company, Inc.)
• Original Assignee: Digeo Incorporated (CommScope Holding Company, Inc.)
• Inventors: McCracken, Thad, Peting, Mark
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US09/784,828
• Publication Number:
  US 20020136062A1
• Time in Patent Office: 677 Days
• Field of Search: 365/189.02, 365/189.05, 365/230.02, 365/233
• US Class Current: 365/189.02
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

The invention provides an efficient structure for synthesized static arrays. Array structures are very common in chip design, and often when doing ASIC design the option of custom-designing these arrays does not exist, therefore necessitating that the arrays be synthesized, placed and routed on silicon in a manner similar to random logic. Standard array structures are not easily synthesized, placed and routed. The invention takes advantage of the case in which the design requirements are such that the array is loaded in whole and then remains static for a period of time. The array implementation writes one column of the array (instead of a row) at a time so that the desired contents of the array are “rotated” 90 degrees before being written to the array. This allows the latches in a column to share a gated clock signal, which allows for an array placement optimized for clock distribution and for general routing density.

Claims

1. A memory array having a plurality of latches organized in columns and rows, the rows storing contiguous bits of data, the memory array comprising:

a first subset of latches representing a first column of data in the memory array coupled to only a first multiplexer to select signals from one of the first subset of latches, the first subset of latches coupled to receive a first clock signal; and

a second subset of latches representing a second column of data in the memory array coupled to only a second multiplexer to select signals from the second subset of latches, the second subset of latches coupled to receive a second clock signal.

2. The memory array of claim 1 further comprising a control circuit to write data from the first column of one or more of the rows to the first subset of latches and to write data from the second column of one or more of the rows to the second subset of latches.

3. The memory array of claim 1 wherein data is written to each of the plurality of latches prior to the data being read from the plurality of latches, and further wherein data is not written to any of the plurality of latches while data is read from any of the plurality of latches.

4. The memory array of claim 1 wherein the plurality of latches are included in an integrated circuit, and further wherein the plurality of latches are designed, at least in part, using automatic place and route software.

5. The memory array of claim 1 further comprising:

a third subset of latches representing a third column of data coupled to a third multiplexer to select signals from one of the third subset of latches, the third subset of latches coupled to receive a third clock signal; and

a fourth subset of latches representing a fourth column of data coupled to a fourth multiplexer to select signals from the fourth subset of latches, the fourth subset of latches coupled to receive a fourth clock signal;

wherein the plurality of latches and the first, second, third and fourth multiplexers are included in an integrated circuit, and further wherein the first, second, third and fourth multiplexers are clustered together.

6. The memory array of claim 1 wherein the plurality of latches stores one of:

instruction data, microcode data and configuration data.

7. A method comprising:

placing a first plurality of latches to store a first column of data in a memory array, the first plurality of latches coupled to only a first multiplexer to select signals from one of the first plurality of latches, the first plurality of latches coupled to receive a first clock signal; and

placing a second plurality of latches to store a second column of data in the memory array, the second plurality of latches coupled to only a second multiplexer to select signals from one of the second plurality of latches, the second plurality of latches coupled to receive a second clock signal.

8. The method of claim 7 further comprising:

writing data from a first column of one or more rows to the first plurality of latches; and

writing data from a second column of one or more of the rows to the second plurality of latches.

9. The method of claim 7 wherein data is written to each of the plurality of latches prior to the data being read from the plurality of latches, and further wherein data is not written to any of the plurality of latches while data is read from any of the plurality of latches.

10. The method of claim 7 wherein the plurality of latches are included in an integrated circuit, and further wherein the plurality of latches are designed, at least in part, using automatic place and route software.

11. The method of claim 7 further comprising:

placing a third plurality of latches to store a third column of data in a memory array, the third plurality of latches coupled to a third multiplexer to select signals from one of the third plurality of latches, the third plurality of latches coupled to receive a third clock signal; and

placing a fourth plurality of latches to store a fourth column of data in the memory array, the fourth plurality of latches coupled to a fourth multiplexer to select signals from one of the fourth plurality of latches, the fourth plurality of latches coupled to receive a fourth clock signal;

wherein the plurality of latches and the first, second, third and fourth multiplexers are included in an integrated circuit, and further wherein the first, second, third and fourth multiplexers are clustered together.

12. The method of claim 7 wherein the plurality of latches stores one of:

instruction data, microcode data and configuration data.

13. A article comprising a machine-readable medium having stored thereon sequences of instructions that, when executed, cause one or more electronic systems to:

place a first plurality of latches to store a first column of data in a memory array, the first plurality of latches coupled to a first multiplexer to select signals from one of the first plurality of latches, the first plurality of latches coupled to receive a first clock signal; and

place a second plurality of latches to store a second column of data in the memory array, the second plurality of latches coupled to a second multiplexer to select signals from one of the second plurality of latches, the second plurality of latches coupled to receive a second clock signal, the first plurality of latches and the second plurality of latches coupled to different multiplexers.

14. The article of claim 13 further comprising sequences of instructions that, when executed, cause the one or more electronic systems to:

write data from a first column of one or more rows to the first plurality of latches; and

write data from a second column of one or more of the rows to the second plurality of latches.

15. The article of claim 13 wherein data is written to each of the plurality of latches prior to the data being read from the plurality of latches, and further wherein data is not written to any of the plurality of latches while data is read from any of the plurality of latches.

16. The article of claim 13 wherein the plurality of latches are included in an integrated circuit, and further wherein the plurality of latches are designed, at least in part, using automatic place and route software.

17. The article of claim 13 further comprising sequences of instructions that, when executed, cause the one or more electronic systems to:

place a third plurality of latches to store a third column of data in a memory array, the third plurality of latches coupled to a third multiplexer to select signals from one of the third plurality of latches, the third plurality of latches coupled to receive a third clock signal; and

place a fourth plurality of latches to store a fourth column of data in the memory array, the fourth plurality of latches coupled to a fourth multiplexer to select signals from one of the fourth plurality of latches, the fourth plurality of latches coupled to receive a fourth clock signal;

wherein the plurality of latches and the first, second, third and fourth multiplexers are included in an integrated circuit, and further wherein the first, second, third and fourth multiplexers are clustered together.

18. The article of claim 13 wherein the plurality of latches stores one of:

instruction data, microcode data and configuration data.

19. A memory array having a plurality of latches organized in columns and rows, the rows storing contiguous bits of data, the memory array comprising:

a first subset of latches representing a first column of data coupled to a first multiplexer to select signals from one of the first subset of latches, the first subset of latches coupled to receive a first clock signal;

a second subset of latches representing a second column of data coupled to a second multiplexer to select signals from the second subset of latches, the second subset of latches coupled to receive a second clock signal; and

a control circuit to write data from the first column of one or more of the rows to the first subset of latches and to write data from the second column of one or more of the rows to the second subset of latches.

20. The memory array of claim 19 wherein data is written to each of the plurality of latches prior to the data being read from the plurality of latches, and further wherein data is not written to any of the plurality of latches while data is read from any of the plurality of latches.

21. The memory array of claim 19 wherein the plurality of latches are included in an integrated circuit, and further wherein the plurality of latches are designed, at least in part, using automatic place and route software.

22. The memory array of claim 19 further comprising:

a third subset of latches representing a third column of data coupled to a third mutliplexer to select signals from one of the third subset of latches, the third subset of latches coupled to receive a third clock signal; and

a fourth subset of latches representing a fourth column of data coupled to a fourth multiplexer to select signals from the fourth subset of latches, the fourth subset of latches coupled to receive a fourth clock signal;

wherein the plurality of latches and the first, second, third and fourth multiplexers are included in an integrated circuit, and further wherein the first, second, third and fourth multiplexers are clustered together.

23. The memory array of claim 19 wherein the plurality of latches stores one of:

instruction data, microcode data and configuration data.