Variable rate modulator

• US 6,498,823 B1
• Filed: 05/12/2000
• Issued: 12/24/2002
• Est. Priority Date: 10/09/1997
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Laskowski, Joseph I., Samueli, Henry
• Primary Examiner(s): Pham, Chi
• Assistant Examiner(s): Bayard, Emmanuel
• Application Number:
  US09/570,238
• Time in Patent Office: 956 Days
• Field of Search: 375/371, 375/372, 375/306, 708/290, 708/251, 708/313, 708/303, 708/847, 327/164, 327/165, 327/172, 327/178, 327/295, 327/296, 331/18, 331/50, 331/46, 331/47
• US Class Current: 375/371
• CPC Class Codes: H04L 27/362 Modulation using more than one carrier, e.g. with quadrature carriers, separately amplitude modulated H04L27/366 takes precedence

Abstract

Digital data signals at a variable input frequency are converted by a numerically controlled oscillator and an interpolator to a signal at a fixed output sampling frequency. The conversion of the variable input frequency to the fixed output sampling frequency may be by a factor other than an integer. The interpolated digital data signals at the fixed output sampling frequency are then modulated into a pair of trigonometric signals at a programmable carrier frequency, one signal having a cosine function and the other signal having a sine function. The modulated signals at the fixed output sampling frequency are then combined to create a modulated signal at a carrier frequency determined by the frequency of the sine and cosine signals. The modulated signal is sampled at the fixed output sampling frequency and converted to a corresponding analog signal using a digital-to-analog converter.

Claims

1. A signal processing system, comprising:

a clock providing a first clock signal at a first clock frequency;

a numerically controlled oscillator responsive to a frequency control signal and the first clock signal for providing an output clock signal at a fixed second clock frequency, and a phase offset signal representing an offset in phase between the first clock signal and the second clock signal, and

an interpolator that offsets a pair of variable frequency input signals in accordance with the phase offset signal to provide an interpolated signal at a fixed output sampling frequency.

2. The signal processing system of claim 1 wherein the phase offset signal is greater than or equal to zero and less than one.

3. The signal processing system of claim 1 wherein the interpolator interpolates the variable frequency input signal by a non-integer value.

4. The signal processing system of claim 1 wherein the interpolator interpolates the variable frequency input signal by an integer value.

5. The signal processing system of claim 1 further comprising a modulator for modulating the interpolated signal onto a trigonometric signal at a carrier frequency.

6. The signal processing system of claim 5 further comprising a digital to analog converter for converting the modulated signal to an analog signal.

7. The signal processing system of claim 1 wherein said interpolator includes a register, responsive to said second clock signal, to provide said pairs of variable frequency input signals.

8. A signal processing system comprising:

a symbol mapper for converting binary data bits to a pair of data signals at a variable frequency having an amplitude and phase that represents the binary data bits;

a clock providing a first clock signal at a first clock frequency;

a numerically controlled oscillator responsive to a control signal and the first clock signal for providing a second clock signal at a fixed second clock frequency, and a phase offset signal representing an offset in phase between the first clock signal and the second clock signal;

an interpolator that offsets a pair of variable frequency input signals in accordance with the phase offset signal to provide interpolated signals at a fixed sampling frequency;

a modulator that modulates the interpolated signals onto trigonometric signals;

an operator that combines the modulated signals; and

a digital to analog converter that converts the combined modulated signal to an analog signal.

9. A method of converting a variable frequency input signal to a fixed frequency output signal comprising:

generating a first clock signal at a first clock frequency;

receiving a frequency control signal that corresponds to a second frequency;

generating a second clock signal at the second frequency as a function of said frequency control signal;

generating a phase offset signal representing an offset in phase between the first clock signal and the second clock signal; and

offsetting a pair of variable frequency data signals in accordance with said phase offset signal to generate an output signal at a fixed sampling frequency.

10. The method of claim 9 further comprising:

modulating the interpolated signal onto trigonometric signals; and

converting the modulated signal to an analog signal.

11. A signal processing system, comprising:

a numerically controlled oscillator responsive to a frequency control signal and a first clock signal at a first clock frequency;

for providing a second clock signal at a fixed second clock frequency, and, for providing a phase offset signal representing an offset in phase between the first clock signal and the second clock signal, and

an interpolator that offsets a pair of variable frequency input signals in accordance with the phase offset signal to provide an interpolated signal at a fixed sampling frequency.

12. A signal processing system comprising:

a symbol mapper for converting binary data bits to a pair of data signals at a variable frequency having an amplitude and phase that represents the binary data bits;

a numerically controlled oscillator responsive to a control signal and a first clock signal at a first clock frequency for providing a second clock signal at a fixed second clock frequency, and a phase offset signal representing an offset in phase between the first clock signal and the second clock signal;

an interpolator that offsets a pair of variable frequency input signals in accordance with the phase offset signal to provide interpolated signals at a fixed sampling frequency;

a modulator that modulates the interpolated signals onto trigonometric signals;

an operator that combines the modulated signals; and

a digital to analog converter that converts the combined modulated signal to an analog signal.

13. A method of converting a variable frequency input signal to an output signal having a fixed output frequency, comprising:

generating a clock signal at a clock frequency equal to baud rate of said input signal as a function of a received frequency control signal;

generating a phase offset signal representing an offset in phase between a recipient clock signal and the clock signal; and

offsetting a pair of variable frequency data signals in accordance with said phase offset signal to generate an output signal at a fixed sampling frequency.

14. A digital resampler comprising:

an interpolator responsive to a symbol clock and a phase offset signal representing an offset in phase between a sample clock at a fixed sampling frequency and said symbol clock, wherein said interpolator offsets a pair of variable frequency input signals in accordance with said symbol clock and phase offset signal to provide an interpolated signal at said fixed sampling frequency.

15. The signal processing system of claim 14 wherein said interpolator comprises a register, responsive to said symbol clock, to provide said pairs of input signals offset by said interpolator.

16. A signal processing system, comprising:

a clock providing a first clock signal at a first clock frequency;

a numerically controlled oscillator responsive to a frequency control signal and the first clock signal for providing a second clock signal at a fixed second clock signal, and a phase offset signal representing an offset in phase between the first clock signal and the second clock signal, and

a linear interpolator responsive to the phase offset signal for converting a variable frequency input signal to an interpolated signal at a fixed sampling frequency.

17. The signal processing system of claim 16 wherein the interpolator provides offsets between a pair of variable frequency input signals in accordance with the phase offset signal.

18. The signal processing system of claim 17 wherein the phase offset signal is greater than or equal to zero and less than one.

19. A signal processing system, comprising:

a clock providing a sample clock signal at a sample clock frequency;

a numerically controlled oscillator responsive to a frequency control signal and the sample clock signal for providing an output clock signal at a fixed output sampling rate, and a phase offset signal representing an offset in phase between the sample clock signal and the output clock signal, and

a linear interpolator that provides offsets between a variable frequency input signal at a first time and a second time in accordance with the phase offset signal to convert provides offsets between a pair of variable frequency input signals in accordance with the phase offset signal the variable frequency input signal to an interpolated signal at a fixed sampling frequency.

20. The signal processing system of claim 19 wherein said linear interpolator comprises a plurality of interpolation stages and wherein at least one of said interpolation stages comprises a non-integer interpolation stage.

21. The signal processing system of claim 19 wherein said interpolator comprises a register, responsive to said output clock signal, to provide said input signal at said first time and second time.

22. The signal processing system of claim 21 further comprising a modulator for modulating the interpolated signal onto a trigonometric signal at a carrier frequency.

23. The signal processing system of claim 22 further comprising an digital to analog converter for converting modulated signal to an analog signal.

24. The signal processing system of claim 19 wherein said linear interpolator comprises a plurality of interpolation stages and wherein at least one of said interpolation stages comprises a register coupled to said variable rate input signal, wherein said register is clocked by said output clock signal at said fixed output sampling rate to provide said input signal at said first time and second time, a difference operator coupled to output of said register and said variable rate input signal, a multiplier coupled to the output of said difference operator for scaling the output of the difference operator in accordance with said phase offset signal and an adder coupled to the output of said register and output of said multiplier for providing said interpolated signal at a Axed sampling frequency.