Control of multiple computer processes using a mutual exclusion primitive ordering mechanism

• US 6,499,048 B1
• Filed: 06/30/1998
• Issued: 12/24/2002
• Est. Priority Date: 06/30/1998
• Status: Expired due to Term

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Williams, Emrys J.
• Primary Examiner(s): Banankhah, Majid A.
• Application Number:
  US09/107,972
• Time in Patent Office: 1,638 Days
• Field of Search: 709/100, 709/101, 709/102, 709/104, 709/107, 709/108, 709/103, 709/105
• US Class Current: 718/102
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Abstract

A program controlled apparatus includes one or more units for executing a multiple process. A mutex ordering mechanism controls the ordering of mutex ownership to provide deterministic execution of the processes. A mutex processor monitors mutex registers for determining mutex ownership. The mutex registers can be configured as sets of mutex request registers and mutex release registers. The apparatus may include a single processor configured to execute multiple processes concurrently, or multiple processing units, each configured to execute one or more processes. A monitor unit which can monitor equivalent operation of the processing sets can also include the mutex ordering mechanism.

Claims

1. Program controlled apparatus comprising:

a plurality of processors, each configured to execute at least one process, and a monitor unit connected to the processors for monitoring equivalent operation of the processors;

at least one resource accessible to the processes of the processors;

at least one mutex for controlling access to the resource; and

the monitor unit comprising a mutex ordering mechanism controlling an ordering of acquisition of the mutex by the processes of the respective processors to provide deterministic execution of the multiple processes.

2. The apparatus of claim 1, wherein the mutex ordering mechanism comprises at least one mutex register and a mutex processor operable to monitor the at least one mutex register for determining mutex ownership.

3. The apparatus of claim 2, wherein the mutex ordering mechanism comprises sets of mutex request registers and mutex release registers.

4. The apparatus of claim 1, comprising a processor configured to process multiple processes concurrently.

5. The apparatus of claim 1, wherein the monitor is connected to receive I/O operations output from the processors, the monitor further being operable to synchronise operation of the processors by signalling the processors on receipt of output I/O operations indicative of a plurality of the processors being at equivalent stage of processing.

6. The apparatus of claim 1, wherein each process or is configured to execute multiple processes concurrently.

7. The apparatus of claim 1 comprising a plurality of processing sets, each processing set comprising a plurality of processors, wherein the monitor unit is operable to monitor equivalent operation of the processing sets.

8. A program controlled apparatus including plural processing means, each processing means being configured to execute at least one process, and monitor means connected to the processing means for monitoring equivalent operation of the processing means, resource means accessible to the processes and at least one mutex means for controlling access to the resource means, the monitor means comprising mutex ordering means for controlling an ordering of acquisition of the mutex means by the processes of the processing means to provide deterministic execution of the multiple processes.

9. Computing apparatus, comprising:

a plurality of processing sets, each including multiple processors, wherein at least a first processing set is operable asynchronously of a second processing set, and a monitor unit connected to the processors for monitoring equivalent operation of the processing sets;

at least one resource for each processing set shared by processors of the processing set; and

at least one mutex for controlling access to said at least one resource;

the monitor unit comprising a mutex ordering mechanism configured to ensure equivalent ordering of acquisition of the mutex by the processors of the processing sets for maintaining deterministic operation of the processing sets.

10. The apparatus of claim 9, wherein the monitor is connected to receive I/O operations output from the processing sets, the monitor further being operable to synchronise operation of first and second processing sets by signalling the processing sets on receipt of output I/O operations indicative of a plurality of the processing sets being at equivalent stage of processing.

11. The apparatus of claim 9, wherein the monitor is operable to compare I/O operations for determining equivalent operating of the processing sets.

12. The system of claim 9, wherein the monitor comprises a voter for determining equivalent ordering of I/O operations and common mutex storage accessed by voted I/O operations.

13. The system of claim 9, wherein the monitor comprises a mutex manager.

14. The system of claim 13, wherein the mutex manager comprises a mutex start register and a mutex stop register per processing set.

15. The system of claim 13, wherein the mutex manager comprises multiple sets of mutex start registers and a hash mechanism for accessing a mutex list for an I/O cycle.

16. A method of providing deterministic execution of programmed processes in a processing system, the processing system comprising a plurality of processors, each processor being operable to execute at least one process, system resources, mutexes which may be selectively owned for controlling access to the system resources, and a monitor unit connected to the processors for monitoring equivalent operation of the processors, the method comprising:

executing the processes in the processors; and

the monitor unit controlling an ordering of mutex acquisition by the processes.

17. The method of claim 16, comprising:

initially executing a process and recording mutex ownership during execution; and

subsequently repeating execution of the process with control of mutex acquisition to correspond to the initial execution of the process.

18. The method of claim 16, further comprising monitoring mutex registers for determining mutex ownership.

19. The method of claim 18, wherein the monitoring step comprises separately monitoring mutex request registers and mutex release registers.

20. A method of providing deterministic operation of an asynchronous multiprocessor computer system which includes a plurality of processors, at least one system resource, a mutex mechanism including at least one mutex which may be selectively owned for controlling access by the processors to the system resource and a monitor unit connected to the processors for monitoring equivalent operation of the processors, the method comprising:

the monitor unit ordering mutex acquisition for access to system resources; and

operating the processors in accordance with the mutex acquisition ordering.