Method of assigning integrated circuit I/O signals in an integrated circuit package

• US 6,499,134 B1
• Filed: 07/13/2000
• Issued: 12/24/2002
• Est. Priority Date: 07/13/2000
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Natonio, Joseph, Buffet, Patrick H., Dunn, Paul E., Proctor, Robert A., Yasar, Gulsun
• Primary Examiner(s): Siek, Vuthe
• Assistant Examiner(s): Levin, Naum B
• Application Number:
  US09/615,149
• Time in Patent Office: 894 Days
• Field of Search: 716/1-21, 716/5, 716/9, 716/12-18
• US Class Current: 716/113
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

A method for improving the crosstalk and time-of-flight performance for signals in an integrated circuit with respect to the package-related wiring. I/O pads in the package-related wiring of a logic design meeting specified crosstalk and time-of-flight constraints are identified using a software tool. The tool produces a graphical display in which the identified I/O pads are highlighted. The tool enables a user to graphically manipulate the display to assign, i.e., establish an electrical connection, between I/O circuits corresponding to the signals and the highlighted I/O pads.

Claims

1. A method comprising:

selecting I/O circuits of a logic design; and

assigning the I/O circuits to I/O pads of a package of the logic design in accordance with a desired crosstalk and time-of-flight constraints for signals corresponding to said I/O circuits associated with the I/O pads.

2. The method of claim 1 wherein the step of assigning includes the steps of:

prioritizing the I/O circuits according to their time-of-flight constraints; and

assigning the I/O circuits to I/O pads of the package of the logic design according to their prioritization.

3. The method of claim 2, wherein said step of assigning includes graphically manipulating I/O circuits corresponding to said signals to position them adjacent to said I/O pads meeting said constraints.

4. A method comprising:

highlighting I/O pads in a graphical display of a logic design layout in accordance with specified crosstalk and time-of-flight constraints; and

assigning I/O circuits to said highlighted I/O pads, said I/O circuits carrying signals to and from said logic design.

5. The method of claim 4, wherein said step of assigning includes manipulating said graphical display to position said I/O circuits adjacent to said highlighted I/O pads.

6. The method of claim 5, wherein a selecting and moving operation is performed with a user interface device to position said I/O circuits.

7. The method of claim 4, wherein said I/O circuits are arranged peripherally to said logic design.

8. A computer-usable medium storing computer-executable instructions which when executed implement a process comprising:

applying specified crosstalk and time-of-flight constraints for signals in a logic design to a database including crosstalk and time-of-flight information for package-related wiring;

identifying I/O pads in said package-related wiring meeting said constraints; and

producing a graphical display of said logic design in which said identified I/O pads are highlighted.

9. The computer-usable medium of claim 8, said process further comprising invoking a graphical tool for manipulating said graphical display, said graphical tool enabling the positioning of said I/O circuits adjacent to said I/O pads.

10. The computer-usable medium of claim 8, said database further including a netlist corresponding to said design, and technology and image rules corresponding to said package-related wiring.

11. A computer system comprising:

a memory containing computer-executable instructions;

a processor coupled to said memory for executing said instructions; and

display means coupled to said processor for generating a graphical display in accordance with said instructions;

wherein;

said graphical display includes an image of a logic design having I/O pads highlighted in accordance with user-specified crosstalk and time-of-flight constraints.

12. The computer system of claim 11, further comprising a user interface for graphically assigning selected I/O circuits of said image to said highlighted I/O pads.

13. The computer system of claim 11, wherein said user interface includes means for manipulating said graphical display to position I/O circuits in said image adjacent to said highlighted I/O pads.

14. The computer system of claim 12, further comprising a design floorplan resulting from a process of graphically assigning said I/O circuits.

15. A method comprising:

highlighting I/O pads, distributed in a die logic area, in a graphical display of a logic design layout in accordance with specified crosstalk and time-of-flight constraints; and

assigning I/O circuits to said highlighted I/O pads, said I/O circuits signals to and from said logic design layout.

16. A method comprising:

highlighting I/O pads, distributed in a die logic area, in a graphical display of a logic design layout in accordance with specified crosstalk and time-of-flight constraints; and

assigning I/O circuits to a range of said highlighted I/O pads, said I/O circuits carrying signals to and from said logic design layout.

17. An apparatus comprising:

means for highlighting I/O pads, distributed in a die logic area, in a graphical display of a logic design layout in accordance with specified crosstalk and time-of-flight constraints; and

means for assigning I/O circuits to said highlighted I/O pads, said I/O circuits carrying signals to and from said logic design layout.

18. An apparatus comprising:

means for highlighting I/O pads, distributed in a die logic area, in a graphical display of a logic design layout in accordance with specified crosstalk and time-of-flight constraints; and

means for assigning I/O circuits to a range of said highlighted I/O pads, said I/O circuits carrying signals to and from said logic design layout.

19. A computer program product comprising;

a computer usable medium having computer readable program code means embodied in the medium, the computer readable program means including;

means for highlighting I/O pads, distributed in a die logic area, in a graphical display of a logic design layout in accordance with specified crosstalk and time-of-flight constraints; and

means for assigning I/O circuits to said highlighted I/O pads, said I/O circuits carrying signals to and from said logic design layout.

20. A computer program product comprising:

a computer usable medium having computer readable program code means embodied in the medium, the computer readable program means including;

means for highlighting I/O pads, distributed in a die logic area, in a graphical display of a logic design layout in accordance with specified crosstalk and time-of-flight constraints; and

means for assigning I/O circuits to arrange of said highlighted I/O pads, said I/O circuits carrying signals to and from said logic design layout.