Beamforming system using analog random access memory

• US 6,500,120 B1
• Filed: 07/31/2001
• Issued: 12/31/2002
• Est. Priority Date: 07/31/2001
• Status: Expired due to Term

• Current Assignee: Fluor Technologies Corporation (Fluor Corporation)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Anthony, Michael P.
• Primary Examiner(s): Jaworski, Francis J.
• Assistant Examiner(s): PATEL, MAULIN M
• Application Number:
  US09/919,524
• Time in Patent Office: 518 Days
• Field of Search: 600/437, 600/447, 600/448, 600/449, 600/455, 600/456, 600/432, 600/442
• US Class Current: 600/437
• CPC Class Codes: G01S 15/8915 using a transducer array
• CPC Class Codes: G01S 7/5208 with integration of processing functions inside probe or scanhead
• CPC Class Codes: G10K 11/346 using phase variation

Abstract

A simple, low cost ultrasound beamforming system uses an analog random access memory (RAM) element for each beamforming channel. The system includes a processor and an ultrasonic transducer array. The ultrasonic transducer array includes a plurality of transducer elements, each transducer element associated with one of a plurality of channels. The system also includes a beamformer adapted to receive an output signal from each of the plurality of transducer elements, and a delay element located in the beamformer and associated with each of the channels, where the delay element comprises an analog random access memory element.

Claims

1. A receive beamformer in an ultrasound imaging system comprising a delay element including analog random access memory (RAM), wherein the delay element further comprises:

a write shift register including a plurality of write shift register memory locations, the write shift register arranged as a circular shift register;

an input line receiving an input analog electrical signal representing a received acoustic signal;

a plurality of write switches connected to said input line, each of the write switches operably controlled by one of the plurality of write shift register memory locations of the write shift register, wherein, when a logical one is in a particular write shift register memory location, the write switch operably controlled by said particular write shift memory location is closed;

a plurality of capacitive elements, each of the capacitive elements connected to one of the plurality of write switches, wherein, when a write switch is closed, the connected capacitive element stores a substantially instantaneous value of the received input electrical signal on the input line;

a read shift register including a plurality of read shift register memory locations, the read shift register arranged as a circular shift register;

a plurality of read switches, each of the read switches connected to one of the plurality of capacitive elements and operably controlled by one of the plurality of read shift register memory locations of the read shift register, wherein, when a logical one is in a particular read shift register memory location, the read switch operably controlled by said particular read shift memory location is closed; and

an output line outputting an output analog electrical signal and connected to said plurality of read switches, wherein, when a read switch is closed, the value of the stored electrical signal on the connected capacitive element is read out to said output line;

wherein the analog RAM is comprised of the input line, the plurality of write switches, the plurality of capacitive elements, the plurality of read switches, and the output line.

2. The delay element of claim 1, wherein each of the plurality of write switches closes in series in response to a logical one shifting through the plurality of the write shift register memory locations and each of the plurality of read switches closes in series in response to a logical one shifting through the plurality of the read shift register memory locations, and wherein there is a delay between the time that the write switch and the read switch connected to the same capacitive element close.

3. The delay element of claim 2, wherein the delay between the time that the write switch and the read switch connected to the same capacitive element close is the focusing steering delay applied to the received input electrical signal.

4. The delay element of claim 3, wherein the delay has a resolution of one sample clock period.

5. The delay element of claim 3, wherein the delay has a resolution of ¼

λ

wherein λ

is the wavelength of the received acoustic signal.

6. The delay element of claim 1, wherein the delay element is one of a plurality of delay elements in the receive beamformer, and wherein an output signal from each of a plurality of ultrasonic transducer elements is applied as an input analog electrical signal to each of the plurality of delay elements located in the receive beamformer.

7. The delay element of claim 2, further comprising:

a stall signal line operably connected to the read shift register, wherein a stall signal causes the logical one to not shift to a next memory location in the read shift register.

8. The delay element of claim 6, wherein a length of the write shift register is such that a total time it takes for a logical one to circularly shift back to the same memory location is greater than a maximum delay time between channels to accommodate adequate focusing and steering of a received beam, wherein a channel is an output signal of a single transducer element, and each of the plurality of delay elements receive one channel.

9. A method of receive beamforming using analog random access memory (RAM) in a delay element, the method comprising:

circulating a logical one through each of a plurality of memory locations in a write shift register arranged as a circular shift register, wherein, when the logical one is in a particular write shift register memory location, a corresponding one of a plurality of write switches connected to an input line closes, thereby latching a substantially instantaneous analog value of the input line in one of a plurality of capacitive elements, the one of the plural capacitive elements being connected to the closed write switch; and

circulating a logical one through each of a plurality of memory locations in a read shift register arranged as a circular shift register, wherein, when the logical one is in a particular read shift register memory location, a corresponding one of a plurality of read switches connected to one of the plural capacitive elements closes, thereby latching, to an output line, a stored analog value in the connected one of the plurality of capacitive elements.

10. The method of claim 9, further comprising:

asserting a stall signal on a stall signal line operably connected to the read shift register, wherein the stall signal causes the logical one circulating through the read shift register to not shift to the next memory location in the read shift register.

11. A computer readable medium having a program for beamforming a received ultrasound signal using analog random access memory (RAM), the program comprising logic for:

controlling a write shift register including a plurality of write shift register memory locations, the write shift register arranged as a circular shift register, wherein the write shift register controls a plurality of write switches connected to an input line, each of the write switches operably controlled by one of the plurality of write shift register memory locations of the write shift register, wherein, when a logical one is in a particular write shift register memory location, the write switch operably controlled by said particular write shift memory location is closed; and

controlling a read shift register including a plurality of read shift register memory locations, the read shift register arranged as a circular shift register, wherein the read shift register controls a plurality of read switches, each of the read switches operably controlled by one of the plurality of read shift register memory locations of the read shift register, wherein, when a logical one is in a particular read shift register memory location, the read switch operably controlled by said particular read shift memory location is closed;

wherein the analog RAM comprises the plurality of write switches, the plurality of read switches, and a plurality of capacitive elements, wherein each capacitive element is connected to one of the plurality of write switches and one of the plurality of read switches, wherein, when a write switch is closed, the connected capacitive element stores a substantially instantaneous value of the received input electrical signal on the input line, and wherein, when a read switch is closed, the value of the stored electrical signal on the connected capacitive element is read out to an output line.