Addressable fuse array for circuits and mechanical devices

• US 6,501,107 B1
• Filed: 12/01/1999
• Issued: 12/31/2002
• Est. Priority Date: 12/02/1998
• Status: Expired due to Fees

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Sinclair, Michael J., Levitan, Jeremy A.
• Primary Examiner(s): Abraham, Fetsum
• Application Number:
  US09/452,886
• Time in Patent Office: 1,126 Days
• Field of Search: 257/208-209, 257/529, 257/210-211
• US Class Current: 257/209
• CPC Class Codes: B81B 3/0086 Electrical characteristics, e.g. reducing driving voltage, improving resistance to peak voltage
• CPC Class Codes: B81B 7/0012 Protection against reverse engineering, unauthorised use, use in unintended manner, wrong insertion or pin assignment
• CPC Class Codes: H01L 23/5256 comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A fuse array having a plurality of fusible links that can be addressed by two electrodes is disclosed. The fuse array includes two conductive strips having the plurality of fusible links located therebetween and electrically coupled to the conductive strips. The fusible links have different electrical resistance and each fusible link includes a fuse portion. A voltage potential applied across the conductive strips induces current flow through the fusible links in accordance with Ohm'"'"'s law and ohmic heating occurs at the fuse portion in proportion to the square of the current. The voltage is increased to cause sufficient ohmic heating to occur in the most conductive fusible link (the fusible link having the lowest electrical resistance) so that the fuse portion in that fusible link fuses. Because the fusible links are connected in parallel to the conductive strips, an equivalent resistance of the plurality of fusible links increases and the current flow diminishes so that no further fuse portions are fused at the selected voltage level. Thereafter, the voltage level may be increased to fuse the most conductive fusible link remaining that is not fused. The fuse array may be incorporated into a circuit as a resistor that can be tuned to circuit requirements or as a physical structure in MEMS devices wherein the fuse array may be tuned to change physical properties of the MEMS device.

Claims

1. A fuse array, comprising:

first and second fusible links that have first and second resistances, respectively, wherein the first resistance is less than the second resistance, and the first and second fusible links have respective first and second fuse portions; and

first and second electrical pads electrically coupled to the first and second fusible links, and wherein a first voltage potential difference across the first and second pads causes a first electrical current to be conducted in the first fusible link and a second electrical current to be conducted in the second fusible link, such that the first fuse portion of the first fusible link fuses.

2. The fuse array of claim 1 wherein a second voltage potential across the first and second electrical pads causes the second fuse portion of the second fusible link to fuse.

3. The fuse array of claim 1 further comprising a third fusible link that is electrically coupled to the first and second electrical pads, the third fusible link having a third resistance and a third fuse portion, and wherein the third resistance is greater than the second resistance and wherein a third voltage potential causes the third fuse portion of the third fusible link to fuse.

4. The fuse array of claim 3 wherein the difference in resistance between the first and second resistances is substantially equal to the difference in resistance between the second and third resistances.

5. The fuse array of claim 3 wherein the difference in resistance between the first and second resistances is not equal to the difference in resistance between the second and third resistances.

6. The fuse array of claim 1 further comprising a substrate and wherein the first pad is fixed coupled to a substrate and the first and second fusible links are fixedly coupled to the first pad and wherein the second pad is a mass coupled to the first and second fusible links and is not fixedly coupled to the substrate.

7. The fuse array of claim 1 wherein the first pad is a mass and the second pad is a mass and the first and second fusible links are fixedly coupled the first and second pads and moving the first pad induces forces in the first and second fusible links and the first and second fusible links transfer forces to the second pad and fusing the fuse portion of the first fusible link changes the forces transferred to the second pad when the first pad is moved.

8. The fuse array of claim 1, further comprising a first electrostatic comb drive that moves the first pad and wherein the first and second fusible links transfer forces from the first pad to the second pad when the first comb drive moves the first pad and wherein fusing the fuse portion of the first fusible link alters the transfer of forces from the first pad to the second pad when the comb drive moves the first pad.

9. The fuse array of claim 1 further comprising a substrate and a mass, and wherein the mass can move relative to the substrate when outside forces act on the mass, and wherein the first and second pads are fixedly coupled to the substrate and the mass is fixedly coupled to the first and second fusible links such that the outside force induces a first motion to the mass when neither fuse portion is fused and the outside force induces a second motion when the first fuse portion is fused.

10. A fuse array, comprising:

first and second fusible links that have first and second resistances, respectively, wherein the first resistance is less than the second resistance, and the first and second fusible links have respective first and second fuse portions; and

first and second electrical pads electrically coupled to the first and second fusible links, and wherein a first voltage potential difference across the first and second pads causes a first electrical current to be conducted in the first fusible link and a second electrical current to be conducted in the second fusible link, such that the first fuse portion of the first fusible link fuses;

wherein the first and second fusible links each comprise a first portion having a first conductivity and a second portion having a second conductivity wherein the first conductivity is greater than the second conductivity, and wherein the second portion of the first fusible link is shorter than the second portion of the second fusible link.

11. The fuse array of claim 10 wherein the first and second portions are doped semiconductors.

12. The fuse array of claim 10 wherein the first portion of the first and second fusible links includes a metallic layer.

13. The fuse array of claim 10 wherein the second portion of the first and second fusible links comprises a polysilicon semiconductor.

14. The fuse array of claim 10 wherein the first portion of the first and second fusible links comprises a polysilicon semiconductor having a metallic portion along a length thereof, and the second portion of the first and second fusible links comprises a polysilicon semiconductor having no metallic portion thereon.

15. An addressable fuse array, comprising:

a first electrically conductive electrode;

a second electrically conductive electrode;

a first fusible link coupled to the first and second electrodes, the first fusible link having a first resistance;

a second fusible link coupled to the first and second electrodes, the second fusible link having a second resistance wherein the second resistance is greater than the first resistance;

whereby a voltage potential applied across the first and second electrodes induces a current in the first and second fusible links and at a first voltage potential the first fusible link becomes non-conducting and the second fusible link remains conducting.

16. The addressable fuse array of claim 15 further comprising a third fusible link coupled to the first and second electrodes, the third fusible link have a third resistance that is greater than the second resistance.

17. The addressable fuse array of claim 16 wherein the difference in resistance between the second resistance and the first resistance is substantially equal to the difference in resistance between the third resistance and the second resistance.

18. The programmable fuse array of claim 16 wherein the difference in resistance between the second resistance and the first resistance is not equal to the difference in resistance between the third resistance and the second resistance.

19. The addressable fuse array of claim 16 wherein at a second voltage potential the second fusible link becomes non-conducting and the third fusible link remains conducting.

20. The addressable fuse array of claim 15 wherein the first and second fusible links each comprise a highly conductive portion and a relatively resistive portion and the length of the relatively resistive portion of the first fusible link is longer than the relatively resistive portion of the second fusible link thereby making the first resistance to be less than the second resistance.

21. The addressable fuse array of claim 20 wherein the highly conductive portions include a strip of conductive metal.

22. The addressable fuse array of claim 15 wherein the first and second fusible links each include a fuse portion and the first voltage potential fuses the fuse portion of the first fusible link.

23. The addressable fuse array of claim 22 further comprising a substrate and wherein the first and second fusible links are supported by the substrate and the fuse portions are suspended above the substrate.

24. The addressable fuse array of claim 22 wherein the fuse portions are convolute.

25. The addressable fuse array of claim 22 wherein the first and second fusible links are symmetrical about a centerline and a left portion of each respective first and second fusible link is located to a left side of the centerline and a right portion of each respective first and second fusible link is located to a right side of the centerline and the left and right portions include elongate portions that terminate in a crook and the left portion is coupled to the right portion at their respective crooks and the first and second fuse portions are the respective coupled crooks.

26. A resonator having a first movable mass wherein the addressable fuse array of claim 15 is coupled to the mass so as to apply a bias force to the mass when the mass moves and wherein the application of the first voltage potential across the first and second electrodes makes the first fusible link non-conducting and lessens the bias force applied to the mass when the mass moves.

27. A resonator having first and second movable masses and wherein the addressable fuse array of claim 15 is coupled to the first and second movable masses so as to transmit coupling forces from the first mass to the second mass when the first mass moves, and wherein making the first fusible link non-conducting lessens the coupling force that is transmitted from the first mass to the second mass when the first mass moves.

28. An addressable fuse array, comprising:

a first electrical conductor;

a second electrical conductor;

a first fusible link coupled to the first and second conductors, the first fusible link comprising a first portion having a first resistance and a length L1, a second portion having a second resistance and a length of length L2, and a third portion, and wherein the first resistance is less than the second resistance; and

a second fusible link coupled to the first and second conductors, the second fusible link comprising a first portion having the first resistance and having a length L3, a second portion having the second resistance and having a length L4, and a third portion;

wherein the length L1 is not equal to the length L3 and the length L2 is not equal to the length L4 thereby making the first fusible link more conductive than the second fusible link, so that a first applied voltage across the first and second electrical conductors causes an electrical current in the first and second fusible links that induces a first ohmic heat in the first fusible link that fuses the third portion of the first fusible link.

29. The addressable fuse array of claim 28 further including a substrate and a mass that is movable relative to the substrate, and wherein the first and second fusible links have a first end coupled to the mass and a second end coupled to the substrate and the first and second fusible links apply a first bias force to the mass when the mass moves and after the first fusible link fuses, the second fusible link applies a second bias force to the mass when the mass moves.

30. The addressable fuse array of claim 28 further including a first and a second mass and wherein the first and second fusible links have a first end coupled to the first mass and a second end coupled to the second mass such that when the first mass moves the first and second fusible links apply a first coupling force to the second mass before the first fusible link is fused and the second fusible link applies a second coupling force to the second mass after the first fusible link is fused.

31. The addressable fuse array of claim 28 wherein the respective first portions of the first and second fusible links includes a metallic strip thereon.

32. The addressable fuse array of claim 28, wherein a centerline is defined as extending laterally through the first fusible link and the second fusible link at an approximate longitudinal midpoint of the first and second fusible links, and wherein the respective first portions of the first and second fusible links comprise a left first portion and a right first portion that are located on respective left and right sides of the centerline.

33. The addressable fuse array of claim 28, wherein a centerline is defined as extending laterally through the first fusible link and the second fusible link at an approximate longitudinal midpoint of the first and second fusible links, and wherein the respective second portions of the first and second fusible links comprise a left second portion and a right second portion that are located on respective left and right sides of the centerline.

34. The addressable fuse array of claim 28, wherein a centerline is defined as extending laterally through the first fusible link and the second fusible link at an approximate longitudinal midpoint of the first and second fusible links, and wherein the respective third portions of the first and second fusible links are located along the centerline.

35. The addressable fuse array of claim 28 further comprising a third fusible link including a first portion having the first resistance and having a length L5, and a second portion having the second resistance and having a length L6, and a third portion.

36. The addressable fuse array of claim 35 wherein a second applied voltage across the first and second electrical conductors after the first fusible links is fused causes an electrical current in the second and third fusible links that induces a second ohmic heat in the second fusible link that fuses the third portion of the second fusible link.

37. The addressable fuse array of claim 35 wherein the difference between the lengths L1 and L3 is substantially the same as the difference between the lengths L3 and L5.

38. The addressable fuse array of claim 35 wherein the difference between the lengths L1 and L3 is not equal to the difference between the lengths L3 and L5.

39. The addressable fuse array of claim 35 wherein the difference between the lengths L2 and L4 is substantially the same as the difference between the lengths L4 and L6.

40. The addressable fuse array of claim 35 wherein the difference between the lengths L2 and L4 is not equal to the difference between the lengths L4 and L6.

41. The addressable fuse array of claim 28 wherein the respective second and third portions of the first and second fusible links are of unitary construction.

42. The addressable fuse array of claim 28 wherein the respective first and second portions of the first and second fusible links are of unitary construction and the first portion includes a metal strip thereon.

43. The addressable fuse array of claim 28 wherein the respective third portions of the first and second fusible links are convolute.

44. The addressable fuse array of claim 28 further comprising a substrate and wherein the respective first and second portions of the first and second fusible links are located on the substrate and the respective third portions of the first and second fusible links are suspend above the substrate.

45. The addressable fuse array of claim 28 wherein the first and second fusible links are polysilicon structures formed on a substrate.

46. The addressable fuse array of claim 28 wherein the first and second fusible links are metal structures formed on a substrate.

47. A fuse array, comprising first and second conductive pads and a plurality of fusible links having different values of resistance, wherein the fusible links are electrically coupled in parallel arrangement to the first and second pads such that a current flowing from the first pad to the second pad passes through each fusible link and wherein a first current blows at least one fusible link so that the at least one fusible link does not conduct current, and the first current does not blow all the fusible links.

48. The fuse array of claim 47, wherein fusible links are elongate and the plurality of fusible links are substantially arranged parallel to one another and located substantially within a same plane.

49. The fuse array of claim 47, further comprising a planar substrate and wherein the fusible links each comprise a first portion located on the planar substrate and a second portion that is spaced apart from the planar substrate and further comprising a member extending between the first portion and the second portion.

50. The fuse array of claim 47, wherein the first and second pads are elongate and located on a same plane and the fusible links extend between the first and second pads on the plane and wherein each fusible link includes a fuse portion that physically breaks when that fusible link is blown.

51. The fuse array of claim 47, wherein the first and second pads are elongate and the first pad is located on a planar substrate and the second pad is space apart from the substrate and the first pad, and the fusible links each include a first portion having a proximal end coupled to the first pad and a second portion having a proximal end coupled to the second pad, and wherein distal ends of the first and second portions of the fusible links are coupled.

52. The fuse array of claim 51, wherein the distal ends of the first and second portions of the fusible links are coupled by a pillar that is substantially elongate and is longitudinally orthogonal to the substrate.

53. The fuse array of claim 47, wherein the fusible links are provided with different resistance values by metallic strips coupled to the fusible links and wherein the metallic strips are arranged as different lengths.

54. The fuse array of claim 47, wherein the first and second pads are elongate and the first pad is located on a planar substrate and the second pad is space apart from the substrate and the first pad, and the fusible links each include a first portion having a proximal end coupled to the first pad and a second portion having a proximal end coupled to the second pad and wherein distal ends of the first and second portions of the fusible links are coupled, and wherein the fusible links are provided with different resistance values by metallic strips coupled to the second portions of the fusible links and wherein the metallic strips are arranged as different lengths.

55. The fuse array of claim 47, further comprising a substrate, and further comprising a conductive mass located proximate the substrate and movable relative to the substrate, and wherein first ends of the fusible links are fixedly coupled to the substrate and second ends of the fusible links are fixedly coupled to the mass for movement therewith such that the fusible links provide a first constraint force to the mass, and wherein the first current blows at least one fusible link so as to provide a second constraint force to the mass.

56. The fuse array of claim 55, wherein a second current lows at least one fusible link that has not been previously blown and the plurality of fusible links provide a third constraint force to the mass.

57. The fuse array of claim 47, wherein the first and second pads are elongate and longitudinal axes of the pads are arranged substantially parallel to one another.

58. The fuse array of claim 47, wherein the first and second pads are elongate and longitudinal axes of the pads are arranged substantially orthogonal to one another.

59. The fuse array of claim 47, further comprising a second plurality of fusible links having values of resistances that substantially match the values of resistances of said plurality of fusible links such that each one of said plurality of fusible links and a respective one of the second plurality of fusible links form a fuse link pair having substantially equal resistance values, and wherein the first current blows at least a first fuse link pair.

60. The fuse array of claim 59, wherein a second current blows a second fuse link pair.