Insulated gate transistor and the method of manufacturing the same

• US 6,501,128 B1
• Filed: 07/05/2000
• Issued: 12/31/2002
• Est. Priority Date: 07/05/1999
• Status: Active Grant

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Otsuki, Masahito
• Primary Examiner(s): Wilson, Allan R.
• Assistant Examiner(s): NGUYEN, JOSEPH H
• Application Number:
  US09/610,052
• Time in Patent Office: 909 Days
• Field of Search: 257/330, 257/332, 257/335, 257/336, 257/339, 257/341, 257/342, 257/343
• US Class Current: 257/330
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/6634 with a recess formed by etching in the source/emitter contact region H01L29/66348 takes precedence; etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

An IGBT that exhibits a low on-voltage and a sufficient short circuit withstand capability and to provide a method of manufacturing such an IGBT. The p-type well region and the n-type emitter region are not formed by the self-alignment technique using the gate electrode as a common mask but by distributing the impurity ions using masks, the edges thereof being displaced for an offset length, by that the channel region is widened. The preferable offset length d is from 0.5 to 5.0 μm.

Claims

1. An insulated gate transistor comprising:

a lightly doped drift layer of a first conductivity type;

a well region of a second conductivity type in the surface portion of the drift layer having a first diffusion depth;

an emitter region of the first conductivity type in the well region;

an extended portion of the well region, which is extended beyond the emitter region, formed along the surface portion of the drift layer, and having a second diffusion depth which is shallower than that of the first depth;

a channel region in the extended portion of the well region extended between the emitter region and the drift layer;

a gate electrode above the extended portion of the well region with a gate oxide film interposed therebetween;

an emitter electrode in common contact with the well region and the emitter region;

a collector electrode on the back surface of the drift layer; and

an offset portion introduced into the extended portion of the well region for expanding the width of the channel region,

wherein the width of the offset portion is from 0.5 to 5.0 μ

m, and

wherein the impurity concentration beneath the surface of the extended portion of the well region is constant for the width of 0.5 μ

m or more.

2. An insulated gate transistor comprising:

a lightly doped drift layer of a first conductivity type;

a well region of a second conductivity type in the surface portion of the drift layer having a first diffusion depth;

an emitter region of the first conductivity type in the well region;

an extended portion of the well region which is extended beyond the emitter region, is formed along the surface portion of the drift layer, and has a second diffusion depth which is shallower than that of the first depth;

a channel region in the extended portion of the well region extended between the emitter region and the drift layer;

a gate electrode above the extended portion of the well region with a gate oxide film interposed therebetween;

an emitter electrode in common contact with the well region and the emitter region;

a collector electrode on the back surface of the drift layer; and

an offset portion introduced into an extended portion of the well region, whereby to expand the width of the channel region;

wherein the impurity concentration beneath the surface of the extended portion of the well region is constant for a width of 0.5 μ

m or more.