High-voltage transistor with buried conduction layer

• US 6,501,130 B2
• Filed: 06/20/2002
• Issued: 12/31/2002
• Est. Priority Date: 01/24/2001
• Status: Expired due to Term

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Power Integrations Incorporated
• Inventors: Disney, Donald Ray
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Tran, Long K.
• Application Number:
  US10/176,345
• Publication Number:
  US 20020149052A1
• Time in Patent Office: 194 Days
• Field of Search: 257/341-346, 257/104, 257/372, 257/375, 257/376, 257/548-550, 438/301-306, 438/299, 438/180, 438/140, 438/188, 438/514, 438/995
• US Class Current: 257/342
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A lateral, high-voltage, FET having a low on-resistance and a buried conduction layer comprises a P-type buried layer region within an N-well formed in a P-type substrate. The P-type buried layer region is connected to a drain electrode by a first P-type drain diffusion region that is disposed in the N-well region. The P-type buried layer region is also connected to a second P-type drain diffusion region that extends down from the surface at one end of the PMOS gate region. A P-type source diffusion region, which connects to the source electrode, defines the other end of the gate region.

Claims

1. A complementary device that includes first and second high-voltage field-effect transistors (HVFETs) fabricated on a substrate of a first conductivity type, comprising:

first and second well regions of a second conductivity type, opposite to the first conductivity type, disposed in the substrate, the first well region being spaced-apart from the second well region, the first and second well regions being associated with the first and second HVFETs, respectively;

the first HVFET further comprising;

a first source diffusion region of the first conductivity type disposed in the first well region;

a first drain diffusion region of the first conductivity type disposed in the first well region spaced-apart from the first source diffusion region, a first channel region being defined in the first well region between the first source diffusion region and the first drain diffusion region;

a second drain diffusion region of the first conductivity type disposed in the first well region spaced-apart from the first drain diffusion region;

a first buried layer region of the first conductivity type disposed within the first well region, the first buried layer region being connected to both the first and second drain diffusion regions;

a first insulated gate formed over the first channel region;

the second HVFET further comprising;

a second source diffusion region of the second conductivity type disposed in the substrate and spaced-apart from the second well region, a second channel region being defined between the second well region and the second source diffusion region;

a third drain diffusion region of the second conductivity type disposed in the second well region;

a second buried layer region of the first conductivity type disposed within the second well region;

a second insulated gate formed over the second channel region.

2. The complementary device of claim 1 wherein the first buried layer region comprises a plurality of buried layers.

3. The complementary device of claim 2 wherein the first drain diffusion region is connected to each of the plurality of buried layers.

4. The complementary device of claim 3 wherein the second drain diffusion region is connected to each of the plurality of buried layers.

5. The complementary device of claim 1 wherein the first conductivity type is P-type and the second conductivity type is N-type.

6. The complementary device of claim 1 wherein the first drain diffusion region is doped at a slightly higher concentration relative to a doping of the first well region.

7. The complementary device of claim 1 wherein the second buried layer region is spaced-apart from the third drain diffusion region.

8. A complementary device fabricated on a substrate of a first conductivity type, comprising:

a first HVFET, which comprises;

a first well region of a second conductivity type, opposite to the first conductivity type, disposed in the substrate;

a first source diffusion region of the first conductivity type disposed in the first well region;

a first drain diffusion region of the first conductivity type disposed in the first well region spaced-apart from the first source diffusion region, a first channel region being defined in the first well region between the first source diffusion region and the first drain diffusion region;

a second drain diffusion region of the first conductivity type disposed in the first well region spaced-apart from the first drain diffusion region;

a first buried layer region of the first conductivity type disposed within the first well region, the first buried layer region being connected to both the first and second drain diffusion regions;

a first insulated gate formed over the first channel region;

a second HVFET, which comprises;

a second well region of the second conductivity type disposed in the substrate;

a second source diffusion region of the second conductivity type disposed in the substrate and spaced-apart from the second well region, a second channel region being defined between the second well region and the second source diffusion region;

a third drain diffusion region of the second conductivity type disposed in the second well region;

a second buried layer region of the first conductivity type disposed within the second well region;

a second insulated gate formed over the second channel region.

9. The complementary device of claim 8 wherein the second well region is spaced-apart from the first well region.

10. The complementary device of claim 8 wherein the first buried layer region comprises a plurality of buried layers.

11. The complementary device of claim 10 wherein the first and second drain diffusion regions are connected to each of the plurality of buried layers.

12. The complementary device of claim 8 wherein the first conductivity type is P-type and the second conductivity type is N-type.

13. The complementary device of claim 8 wherein the second buried layer region is spaced-apart from the third drain diffusion region.