Topographical electrostatic protection grid for sensors

• US 6,501,142 B2
• Filed: 04/25/2001
• Issued: 12/31/2002
• Est. Priority Date: 12/30/1998
• Status: Expired due to Term

• Current Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Fang, Ming, Thomas, Danielle A.
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): VOCKRODT, JEFF B
• Application Number:
  US09/843,260
• Publication Number:
  US 20020047161A1
• Time in Patent Office: 615 Days
• Field of Search: 257/414, 257/415, 257/532, 382/124
• US Class Current: 257/414
• CPC Class Codes: G06V 40/1329 Protecting the fingerprint sensor against damage caused by the finger

Abstract

A structure and method for dissipating charges comprising an underlying dielectric layer disposed over capacitor plates of sensor circuitry a gap being formed conformally between adjacent plates and a topographic discharge grid over the underlying dielectric layer and wherein the topographic discharge grid fills at least a portion of the gap between the plates over the dielectric layer and diffuses electrostatic charges at the surface of the integrated circuit.

Claims

1. A portion of an integrated circuit, comprising:

an insulating layer between and over a plurality of conductive plates, wherein a gap is formed between the portions of the insulating layer over adjacent conductive plates; and

a conductive electrostatic topographic discharge grid disposed, in the area over the conductive plates, only in the gap.

2. The integrated circuit of claim 1, wherein the insulating layer further comprises a passivation layer to protect the conductive plates from damage.

3. A portion of an integrated circuit, comprising:

a conformal dielectric layer over a plurality of conductive plates, the dielectric layer isolating the conductive plates and having lower topographic regions between adjacent plates; and

a topographic discharge grid disposed over at least a portion of the dielectric layer in the lower topographic regions between adjacent plates but not over portions of the dielectric layer over the conductive plates, wherein the topographic discharge grid dissipates an electrostatic charge in a manner that prevents the electrostatic charge from reaching the plurality of conductive plates.

4. The integrated circuit of claim 3, further comprising:

a passivation layer disposed over a portion of a conductive plate and the topographic discharge grid.

5. The integrated circuit of claim 3, wherein the topographic discharge grid has a sheet resistance low enough to adequately dissipate the electrostatic charge.

6. The integrated circuit of claim 3, wherein the topographic discharge grid comprises aluminum.

7. The integrated circuit of claim 3, wherein the topographic discharge grid has a thickness of between approximately 5,000 to 15,000 angstroms.

8. The integrated circuit of claim 3, wherein the topographic discharge grid has a resistivity of approximately 0.04 ohms per square.

9. The integrated circuit of claim 3, wherein the topographic discharge grid comprises titanium.

10. The integrated circuit of claim 9, wherein the topographic discharge grid has a thickness of between approximately 500 to 1,000 angstroms.

11. The integrated circuit of claim 9, wherein the topographic discharge grid has a resistivity of approximately 10 ohms per square.

12. The integrated circuit of claim 3, wherein the topographic discharge grid comprises tungsten.

13. The integrated circuit of claim 12, wherein the topographic discharge grid has a thickness of between approximately 4,000 to 8,000 angstroms.

14. The integrated circuit of claim 12, wherein the topographic discharge grid has a resistivity of approximately 0.14 ohms per square.

15. The integrated circuit of claim 12, further comprising:

a passivation layer disposed over at least a portion of the dielectric layer and adjacent the topographic discharge grid.

16. The integrated circuit of claim 15, wherein the topographic discharge grid is disposed over portions of the dielectric layer within an area encompassing substantially all of the conductive plates, and wherein the passivation layer is disposed over substantially all of the dielectric layer not covered by the topographic discharge grid.

17. An integrated circuit structure comprising:

an array of pairs of capacitive sensor plates;

a conformal insulating layer overlying the sensor plates, the insulating layer having lower topographic regions between sensor plates; and

a conductive discharge grid disposed, in an area over the sensor plates, only in the lower topographic regions between sensor plates.

18. The integrated circuit as set forth in claim 17 further comprising:

a passivation layer overlying portions of the insulating layer, the passivation layer disposed between the discharge grid and the insulating layer between adjacent pairs of sensor plates but not between sensor plates forming a pair of sensor plates within the array.

19. The integrated circuit as set forth in claim 18 wherein the passivation layer comprises a material selected from silicon carbide, silicon nitride, and a combination of silicon carbide and silicon nitride.

20. The integrated circuit as set forth in claim 18 wherein the discharge grid is substantially planar with the passivation layer.

21. The integrated circuit as set forth in claim 17 wherein the discharge grid comprises a material selected from aluminum, titanium and tungsten.