Ring oscillators with improved signal-path matching for high-speed data communications
DCFirst Claim
1. A ring oscillator comprising:
- a sequence of delay circuits including at least first and second pairs of non-adjacent delay circuits, with each pair of non-adjacent delay circuits having at least one delay circuit between them and with each delay circuit in the sequence having an input for receiving an input signal and an output for driving a delayed version of the input signal into the input of only one other delay circuit in the sequence; and
a first input-output connection between the first pair of non-adjacent delay circuits; and
a second input-output connection between the second pair of non-adjacent delay circuits.
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Abstract
Electronic devices are typically coupled together to operate as systems that require the communication of data from one device to another. Many such devices include a ring oscillator, a circuit that generates one or more oscillating signals using a series of interconnected delay circuits. One problem with conventional ring oscillators concerns differences in the signal paths between the delay circuits. Accordingly, the present inventors devised several oscillators having unique layouts, which reduce differences in the signal paths between delay circuits. One exemplary oscillator includes a sequence of delay circuits having input-output connections between at least two pairs of non-adjacent delay circuits. Another exemplary oscillator provides two groups of delay circuits with a bus between the two groups, intercoupling the circuits. And, another exemplary oscillator arranges three or more delay circuits to form a closed loop. Applications for these oscillators include not only receivers, transmitters, and transceivers, but also programmable integrated circuits, electronic devices, and systems.
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Citations
5 Claims
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1. A ring oscillator comprising:
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a sequence of delay circuits including at least first and second pairs of non-adjacent delay circuits, with each pair of non-adjacent delay circuits having at least one delay circuit between them and with each delay circuit in the sequence having an input for receiving an input signal and an output for driving a delayed version of the input signal into the input of only one other delay circuit in the sequence; and
a first input-output connection between the first pair of non-adjacent delay circuits; and
a second input-output connection between the second pair of non-adjacent delay circuits. - View Dependent Claims (2, 3, 4, 5)
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Specification