Configuration memory architecture for FPGA

• US 6,501,677 B1
• Filed: 04/03/2001
• Issued: 12/31/2002
• Est. Priority Date: 02/25/1998
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Rau, Prasad, Menon, Suresh M, Ghia, Atul V.
• Primary Examiner(s): Zarabian, Amir
• Application Number:
  US09/825,757
• Time in Patent Office: 637 Days
• Field of Search: 365/154, 365/189.12, 365/189.05, 365/156, 326/39
• US Class Current: 365/154
• CPC Class Codes: H03K 19/1776 for memories

Abstract

A configuration memory architecture for an FPGA eliminates the need for a regular array of word lines and bit lines. The memory includes memory bytes, each of which has eight SRAM latches, a single flip-flop and a one-of-eight decoder having data input coupled to the inverting output of the flip-flop and eight individual data outputs, each of which is coupled to a data input of one of the SRAM latches. The flip-flops of all memory bytes for a logic block are coupled together in a serpentine shift register. Loading of configuration data involves shutting down all paths through the decoder, shifting all configuration bits for the “0” position SRAM latch of each memory byte into the shift register, and setting the address bits to the decoder so as to create a conductive path on each memory byte from the output of the flip-flop to the data input of the 0 latch. The process is then repeated for the seven other SRAM latch positions.

Claims

1. A memory cell structure in a field programmable gate array for storing programming bits that define the functionality of said field programmable gate array, comprising:

a plurality of memory cells for storing a plurality of programming bits that define the functionality of said field programmable gate array, said plurality of memory cells divided into a plurality of groups, each memory cell having an input and having an output for coupling to a logic block or other node of said field programmable gate array;

for each said group of memory cells, selective data path forming means having an address input for receiving an address, a single data bit input, and a plurality of outputs, each output coupled to one input of a different memory cell in said group of memory cells, said selective data path means forming a conductive path between said single data bit input and one of said plurality of outputs depending on the address bits received at said address input; and

at least one shift register having a data input and a clock input, for receiving at said data input a string of data bits in serial format which are shifted into said shift register in accordance with clock signals received at said clock input, said shift register comprising a chain of flip-flops, each flip-flop having a clock input, a data input, and at least one data output, wherein the clock input of each flip-flop is coupled to the clock input of said shift register;

the data input of one flip-flop in the chain is coupled to the data input of said shift register;

the data input of every flip-flop other than said one is coupled to a data output of the previous flip-flop in said chain; and

a data output of each flip-flop is coupled to the single data bit input of the selective data path forming means of one of said groups of memory cells.

3. A memory cell structure as in claim 1 in which each flip-flop has one inverting and one non-inverting output, wherein the output coupled to the single data bit input of the selective data path forming means is said inverting output and the data output of the previous flip-flop in said chain is said non-inverting output.

2. A memory cell structure in a field programmable gate array for storing programming bits that define the functionality of said field programmable gate array, comprising:

a plurality of memory cells for storing a plurality of programming bits that define the functionality of said field programmable gate array, said plurality of memory cells divided into a plurality of functional groups of memory cells, each functional group comprising a plurality of subgroups of memory cells, each subgroup having memory cells numbered from one to N which will hereinafter be referred to as a memory byte, each memory cell having an input and having an output for coupling to a logic block or other node of said field programmable gate array;

for each said memory byte of each said subgroup of memory cells, selective data path forming means having an address input for receiving an address, a single data bit input, and a plurality of outputs, each output coupled to one input of a different memory cell in said memory byte, said selective data path means forming a conductive path between said single data bit input and one of said plurality of outputs depending upon the address bits received at said address input; and

a separate shift register for each said functional group, each said shift register having a data input and a clock input, for receiving at said data input a string of programming data bits, said programming data bits received in serial format which are shifted into said shift register in accordance with clock signals received at said clock input, said shift register comprising a chain of flip-flops, each flip-flop having a data input, a clock input, and at least one data output, wherein the clock input of each flip-flop is coupled to the clock input of said shift register;

the data input of one flip-flop in the chain is coupled to the data input of said shift register;

the data input of every flip-flop other than said one is coupled to a data output of the previous flip-flop in said chain; and

a data output of each flip-flop is coupled to the single data bit input of the selective data path forming means of one of said groups of memory cells.

4. A memory cell structure as in claim 2 in which each flip-flop has one inverting and one non-inverting output, wherein the output coupled to the single data bit input of the selective data path forming means is said inverting output and the data output of the previous flip-flop in said chain is said non-inverting output.