Multi-processor mobile computer system having one processor integrated with a chipset

• US 6,501,999 B1
• Filed: 12/22/1999
• Issued: 12/31/2002
• Est. Priority Date: 12/22/1999
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Cai, Zhong-ning
• Primary Examiner(s): Black, Thomas
• Assistant Examiner(s): BARNES-BULLOCK, CRYSTAL JOY
• Application Number:
  US09/470,286
• Time in Patent Office: 1,105 Days
• Field of Search: 700/4-5, 700/2, 700/82, 968/535, 713/320-324, 713/340
• US Class Current: 700/82
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Computer systems having two processors of different clock frequencies and different levels of power consumption. An interface circuit can select one of the two processors to operate at a time to reduce power consumption without compromising the system performance.

Claims

1. A computer system, comprising:

a first processor, operating at a first clock frequency and a first level of power consumption;

a second processor of a second clock frequency and a second level of power consumption, said second clock frequency and second level being respectively less than said first clock frequency and said first level of power consumption; and

an interface circuit, coupled to control said first and second processors to select one processor to operate at a particular time, wherein electric power to said first-processor is turned off when said second processor is selected to operate.

2. A computer system as in claim 1, further comprising a chipset that controls the communication among said first and second processors, wherein said interface circuit is built into said chipset, and wherein said second processor and said chipset are integrated on a single substrate.

3. A computer system as in claim 2, further comprising a system memory, and a graphic controller, wherein said system memory and said graphic controller are integrated with said second processor and said chipset on said single substrate.

4. A computer system as in claim 1, wherein said interface circuit selects only one of said first and second processors to operate at a particular time when AC power is not available.

5. A computer system as in claim 1, wherein said interface circuit maintains power to said second processor when said first processor is selected to operate.

7. A computer system as in claim 1, wherein said interface circuit selects said first processor to execute one or a series of instructions when processing power of said second processor is insufficient to execute said one or series of instructions.

6. A computer system, comprising:

a first processor, operating at a first clock frequency and a first level of power consumption;

a second processor of a second clock frequency and a second level of power consumption, said second clock frequency and second level being respectively less than said first clock frequency and said first level of power consumption; and

an interface circuit, coupled to control said first and second processors to select one processor to operate at a particular time, wherein said first processor is turned off when said second processor is selected to operate, and wherein said interface circuit turns off electric power to said second processor when said first processor is selected to operate.

8. A method of operating two processors in a computer system, comprising:

providing a first processor of a first clock frequency and a first level of power consumption, and a second processor of a second clock frequency and a second level of power consumption, which are respectively less than said first clock frequency and said first level of power consumption;

selecting only one of said first and second processors to operate at a time; and

turning off electric power to said first processor when said second processor is selected to operate.

9. A method of operating two processors in a computer system, comprising:

providing a first processor of a first clock frequency and a first level of power consumption, and a second processor of a second clock frequency and a second level of power consumption, which are respectively less than said first clock frequency and said first level of power consumption;

selecting only one of said first and second processors to operate at a time;

turning off electric power to said first processor when said second processor is selected to operate; and

making data in at least one cache of one processor of said first and second processors available to another processor after said one processor completes execution of one or more instructions and said another processor is to replace said one processor for a subsequent execution.

10. A method as in claim 9, wherein said data in at least one cache of said one processor is saved to a system memory shared by said first and second processors.

11. A method as in claim 10, wherein an interrupt is generated, when said one processor is to be replaced by said another processor for said subsequent execution, to command said one processor to save said data in said system memory.

12. A method as in claim 9, wherein said data from said one processor is directly transferred to said another processor.

13. A method of operating two processors in a computer system, comprising:

providing a first processor of a first clock frequency and a first level of power consumption, and a second processor of a second clock frequency and a second level of power consumption, which are respectively less than said first clock frequency and said first level of power consumption;

selecting only one of said first and second processors to operate at a time;

turning off electric power to said first processor when said second processor is selected to operate; and

establishing a communication between said first and second processors to inform CPU states of one processor of said first and second processors to another processor after said one processor completes execution of one or more instructions and said another processor is to replace said one processor for a subsequent execution.

14. A method as in claim 13, wherein said CPU states of said one processor are saved into a memory accessible to said another processor.

15. A method as in claim 13, wherein said CPU states of said one processor are directly transferred to said another processor.

16. A method as in claim 13, wherein a software routine is used to inform said CPU states of said one processor to said another processor.

17. A computer system, comprising:

a first chip having a first processor of a first clock frequency and a first level of power consumption;

a second chip separate from said first chip and configured to have a second processor of a second clock frequency and a second level of power consumption which are respectively less than said first clock frequency and said first level of power consumption;

a chipset integrated on said second chip to provide communication to and from said first and second processors, said chipset including an interface circuit configured to select one of said first and second processors to operate at a time, wherein electric power to said first processor is turned off when said second processor is selected to operate.

18. A computer system as in claim 17, further comprising a system memory and a graphic controller that are integrated on said second chip.

19. A computer system as in claim 17, further comprising a RAM unit formed on said second chip to store CPU states from said first and second processors.