Fast system and method for producing a logarithmic signal approximation with variable precision

• US 6,502,118 B1
• Filed: 03/22/2001
• Issued: 12/31/2002
• Est. Priority Date: 03/22/2001
• Status: Expired due to Term

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Chatterjee, Manjirnath
• Primary Examiner(s): Malzahn, David H.
• Application Number:
  US09/815,033
• Publication Number:
  US 20030005006A1
• Time in Patent Office: 649 Days
• Field of Search: 708/517, 708/277, 708/512
• US Class Current: 708/517
• CPC Class Codes: G06F 7/556 Logarithmic or exponential functions
• CPC Class Codes: G06F 7/74 Selecting or encoding within a word the position of one or more bits having a specified value, e.g. most or least significant one or zero detection, priority encoders with shifting G06F5/01

Abstract

A system and method for producing an output logarithmic digital signal from an input digital signal having a plurality of bit values in which the output logarithmic signal has a precision defined by a parameter is described. The system (45) includes a search circuit (50), an interpolation circuit (55) in coupled with the search circuit, a shift circuit (60) in coupled with the interpolation circuit and a combiner (65) that produces an output logarithmic digital signal (90) from a received search circuit output (75) and a received shift circuit output (88).

Claims

1. A system for producing an output logarithmic digital signal from an input digital signal having a plurality of bit values wherein the output logarithmic signal has a precision defined by a parameter, the system comprising:

a search circuit;

an interpolation circuit in signal communication with the search circuit;

a shift circuit in signal communication with the interpolation circuit; and

a combiner that produces an output logarithmic digital signal from a received search circuit output and a received shift circuit output.

2. The system of claim 1 wherein the interpolation circuit is a combinational logic circuit capable of calculating a linear interpolation on an output from the search circuit based on the parameter.

3. The system of claim 2 wherein the search circuit is a combinational logic circuit capable of performing a standard binary search on the input digital signal.

4. The system of claim 2 wherein the search circuit is a combinational logic circuit capable of performing a shift and search operation on the input digital signal.

5. The system of claim 1 wherein the search circuit, interpolation circuit, shift circuit and combiner are all integrated in a signal integrated circuit.

6. The system of claim 5 wherein the signal integrated circuit is application specific integrated chip.

7. A system for producing an output logarithmic digital signal from an input digital signal having a plurality of bit values wherein the output logarithmic signal has a precision defined by a parameter, the system comprising:

means for finding a bit position of a highest bit value of the input digital signal;

means for interpolating an interpolation value from the bit position;

means for determining an offset from the interpolation value; and

means for adding the offset and the bit position.

8. The system of claim 7 wherein the interpolating means is a combinational logic circuit capable of calculating a linear interpolation on an output from the finding means based on the parameter.

9. The system of claim 8 wherein the finding means is a combinational logic circuit capable of performing a standard binary search on the input digital signal.

10. The system of claim 8 wherein the finding means is a combinational logic circuit capable of performing a shift and search operation on the input digital signal.

11. A method for producing an output logarithmic digital signal from an input digital signal having a plurality of bit values wherein the output logarithmic signal has a precision defined by a parameter, the method comprising:

searching for a bit position of a highest bit value of the input digital signal;

interpolating an interpolation value from the bit position;

determining an offset from the interpolation value; and

adding the offset with the bit position.

12. The method of claim 11 wherein the step of interpolating further includes calculating a linear interpolation on the highest bit value based on the parameter.

13. The system of claim 12 wherein the step of searching further includes a standard binary search on the input digital signal.

14. The system of claim 12 wherein the step of searching further includes a shift and search operation on the input digital signal.

15. A computer program embodied on a computer-readable medium for producing an output logarithmic digital signal from an input digital signal having a plurality of bit values wherein the output logarithmic signal has a precision defined by a parameter, the computer program comprising:

logic configured for searching for a bit position of a highest bit value of the input digital signal;

logic configured for interpolating an interpolation value from the bit position;

logic configured for determining an offset from the interpolation value; and

logic configured for adding the offset with the bit position.

16. The computer-readable medium of claim 15 wherein the interpolating logic further includes logic configured for calculating a linear interpolation on the highest bit value based on the parameter.

17. The computer-readable medium of claim 16 wherein the searching logic further includes logic configured to perform a standard binary search on the input digital signal.

18. The computer-readable medium of claim 16 wherein the searching logic further includes logic configured to perform a shift and search operation on the input digital signal.