Method and system for address spaces

• US 6,502,158 B1
• Filed: 03/18/2000
• Issued: 12/31/2002
• Est. Priority Date: 04/23/1999
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Inventors: Fairman, Bruce, James, David V.
• Primary Examiner(s): THAI, XUAN MARIAN
• Application Number:
  US09/531,084
• Time in Patent Office: 1,018 Days
• Field of Search: 710/100, 710/300, 710/104, 710/305, 710/306, 710/311
• US Class Current: 710/311
• CPC Class Codes: H04L 12/2803 Home automation networks
• CPC Class Codes: H04L 12/40078 Bus configuration home automation networks H04L12/2803; arrangements for maintenance or administration H04L41/00
• CPC Class Codes: H04L 12/40091 Bus bridging LAN interconnection over a bridge based backbone H04L12/462; single bridge functionality H04L12/462
• CPC Class Codes: H04L 12/40117 Interconnection of audio or video/imaging devices home automation networks H04L12/2803; bitstream network arrangements specially adapted for distribution of digital video signals H04N7/24
• CPC Class Codes: H04L 12/4625 Single bridge functionality, e.g. connection of two networks over a single bridge
• CPC Class Codes: H04L 12/6418 Hybrid transport
• CPC Class Codes: H04L 2012/2849 Audio/video appliances
• CPC Class Codes: H04L 2101/604 Address structures or formats
• CPC Class Codes: H04L 2101/622 Layer-2 addresses, e.g. medium access control [MAC] addresses
• CPC Class Codes: H04L 41/0896 Bandwidth or capacity management, i.e. automatically increasing or decreasing capacities flow or congestion control using dynamic resource allocation, e.g. in-call renegotiation, H04L47/76
• CPC Class Codes: H04L 41/0897 by horizontal or vertical scaling of resources, or by migrating entities, e.g. virtual resources or entities
• CPC Class Codes: H04L 41/12 Discovery or management of network topologies
• CPC Class Codes: H04L 61/00 Network arrangements, protocols or services for addressing or naming
• CPC Class Codes: H04L 61/10 of different types
• CPC Class Codes: H04L 61/5038 for local use, e.g. in LAN or USB networks, or in a controller area network [CAN]
• CPC Class Codes: H04L 61/5046 Resolving address allocation conflicts; Testing of addresses testing when self-assigning an address H04L61/5092
• CPC Class Codes: H04L 61/5053 Lease time; Renewal aspects
• CPC Class Codes: H04L 61/5061 Pools of addresses
• CPC Class Codes: H04L 61/5092 by self-assignment, e.g. picking addresses at random and testing if they are already in use
• CPC Class Codes: H04L 69/22 Parsing or analysis of headers

Abstract

A system for allowing a node to be accessed through multiple address spaces. The system includes a virtual address memory providing a software settable bus identification address and a stable node identification address for each node in a net, a physical address memory providing a physically assigned node identification address for each node in a local bus, and a logical address memory providing a stable node identification address for each node in the local bus.

Claims

1. A system for allowing a node to be accessed through multiple address spaces comprising:

a virtual address memory providing a net refresh managed bus identification address and a stable node identification address for each node in a net;

a physical address memory providing a physically assigned node identification address for each node in a local bus; and

a logical address memory providing a stable node identification address for each node in the local bus.

2. The system of claim 1 wherein the system translates stable node identification addresses to physical node identification addresses to allow access to local nodes using logical addresses.

3. The system of claim 1 wherein the system captures requests and translates logical node identification addresses to physical node identification addresses.

4. The system of claim 1 wherein the system captures responses and translates logical node identification addresses to physical node identification addresses.

5. The system of claim 1 wherein the stable node identification address is a initially assigned node identification address.

6. The system of claim 1 wherein a special portal on a bus is always assigned a fixed stable identification address.

7. The system of claim 6 wherein the special portal is the alpha portal.

8. The system of claim 6 wherein the special portal is the delta portal that does stable identification address to physical identification address translations.

9. The system of claim 1 wherein fixed stable identification addresses are assigned to nodes of interest.

10. The system of claim 1 wherein the stable identification addresses are assigned by a bus bridge.

11. The system of claim 1 wherein the stable identification addresses are recognized by a bus bridge and stored in a register on each node of a bus.

12. The system of claim 1 wherein the stable identification addresses are determined by local bus nodes in a cooperative fashion.

13. A system comprising:

a bus including at least two nodes; and

at least one bus bridge portal comprising

a virtual address space for storing a software settable bus identification address and a stable node identification address for each node in a bus system;

a physical address space for storing a physically assigned node identification address for each node in a local bus; and

a logical address space for storing a stable node identification address for each node in the local bus.

14. The system of claim 13 wherein a portal captures node access requests from a requesting node and translates stable node identification addresses to physical node identification addresses.

15. The system of claim 13 wherein the requesting node stores the stable node identification address to physical node identification address translation in a cache memory in the requesting node.

16. The system of claim 13 wherein the bus is substantially similar to a version of the IEEE 1394 standard serial bus.

17. A bus bridge comprising:

means for accessing nodes through software settable bus identification addresses and stable node identification addresses;

means for accessing nodes through physical node identification addresses on a local bus; and

means for accessing nodes through stable node identification addresses on a local bus.

18. A method for identifying nodes on a bus comprising:

receiving a request to access a node on a bus;

accepting the request if a bus identification portion of a destination address of the request matches a local bus identification address and a local node identification address of the destination address matches a physical node identification address on the local bus;

translating a stable identification address of the destination address to a physical node identification address if the bus identification portion of the destination address matches a logical bus identification address or the bus identification portion of the destination address matches a bus number; and

accepting the request if the translated physical node identification address matches a physical node identification address on the local bus.

19. A method of node identification comprising:

identifying a physical node identification address for a node; and

storing the physical node identification address as a stable node identification address.

20. The method of claim 19 further comprising:

matching a local identification portion of a received destination address to the stable node identification address; and

translating the stable node identification address to a physical node identification address.

21. A memory for storing data for access by a program being executed on a data processing system, comprising:

a data structure stored in a memory, the data structure including information used by a program including;

a virtual address data structure including software settable bus identification addresses for nodes on a net;

a physical address data structure including physically assigned node identification addresses for nodes on a local bus; and

a logical address data structure including stable node identification addresses for nodes on the local bus.