Memory accessing and controlling unit

• US 6,502,172 B2
• Filed: 01/11/2002
• Issued: 12/31/2002
• Est. Priority Date: 03/02/1999
• Status: Expired due to Term

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Chang, Nai-Shung
• Primary Examiner(s): Nguyen, Hiep T.
• Application Number:
  US10/045,433
• Publication Number:
  US 20020059506A1
• Time in Patent Office: 354 Days
• Field of Search: 711/168, 711/118, 711/143, 711/167, 711/169, 711/105
• US Class Current: 711/167
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 13/161 with latency improvement

Abstract

A memory accessing and controlling unit that controls the transfer of data between a CPU and a memory cluster. The memory accessing and controlling unit comprises a CPU interface circuit and a memory controlling circuit. When the CPU interface circuit picks up a data read request signal from the CPU, a corresponding internal data read request is forwarded to the memory controlling circuit. Next, the memory controlling circuit is sent out some controlling instructions to the memory cluster for reading out the requested data to the CPU. If the CPU also sends out an L1 write-back signal some time later, the memory controlling circuit immediately terminates the current reading operation so that data from the CPU can be written back to the memory cluster.

Claims

1. A memory access control system for controlling a memory access operation suitable for use between a CPU and a memory unit, wherein the CPU can issue a read request and issue an L1 write-back signal after a predetermined time to indicate that a write back operation is desired, the memory access control system comprising:

a CPU interface circuit coupled to the CPU, wherein when the CPU interface circuit receives the read request from the CPU, an internal read request is issued without waiting for the L1 write-back signal, wherein when the CPU interface circuit receives the L1 write-back signal, a read-stop signal is promptly issued; and

a memory control unit coupled between the CPU interface circuit and the memory unit, wherein when the memory control unit receives the internal read request from the CPU interface circuit, a read operation is accordingly performed, and when the memory control unit receives the read-stop signal, the read operation stops and the write back operation accordingly starts.

2. The system of claim 1, wherein when the read operation stops, read-out data from the memory unit are discarded.

3. The system of claim 1, wherein the memory cluster includes a synchronous dynamic random access memory (SDRAM).

4. The system of claim 1, wherein when the memory control unit receives the internal read request, the internal read request is activated after a previous data access operation is complete.

5. The system of claim 1, wherein the read-stop signal is issued at a next clock cycle when the CPU interface circuit receives the L1 write-back signal.

7. The method of claim 5, further comprising:

discarding read-out data by the internal data reading operation after the step of stopping the current internal data reading operation; and

performing the write-back operation.

8. The method of claim 5, wherein the read-stop signal is issued at a next clock cycle when the L1 write-back signal is received.

6. A memory access control method suitable for controlling a CPU to access data in a memory unit, wherein a read request is issued by the CPU and an L1 write-back signal is also issued after a certain period of time if a write-back operation is desired, the memory access control method comprising:

performing an internal data reading operation without waiting for the L1 write-back signal when the read request is received;

promptly issuing a read-stop signal when the L1 write-back signal is received; and

stopping the current internal data reading operation when the L1 write-back signal is issued and received.