Microcomputer debug architecture and method
First Claim
1. A computer system comprising:
- at least one central processing unit;
a memory unit coupled to the at least one central processing unit;
a set of watchpoints defined in the computer system, each watchpoint in the set of watchpoints comprising;
a programmable precondition register that stores a set of precondition codes, wherein the set of precondition codes is identical for each watchpoint in the set of watchpoints;
a programmable action register that stores a set of action codes, wherein the set of action codes is identical for each watchpoint in the set of watchpoints; and
a first comparator, having inputs coupled to the precondition register, that compares at least one precondition code in the set of precondition codes with a first data value in the computer system and provides a signal to the action register in response thereto.
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Abstract
A computer system including at least one central processing unit, a memory unit coupled to the at least one central processing unit, a set of watchpoints a set of watchpoints defined in the computer system, each watchpoint in the set of watchpoints including a programmable precondition register that stores a set of precondition codes, wherein the set of precondition codes is identical for each watchpoint in the set of watchpoints and a programmable action register that stores a set of action codes, wherein the set of action codes is identical for each watchpoint in the set of watchpoints, and a first comparator, having inputs coupled to the precondition register, that compares at least one precondition code in the set of precondition codes with a first data value in the computer system and provides a signal to the action register in response thereto. A method of triggering a watchpoint in a computer system is also provided.
96 Citations
26 Claims
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1. A computer system comprising:
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at least one central processing unit;
a memory unit coupled to the at least one central processing unit;
a set of watchpoints defined in the computer system, each watchpoint in the set of watchpoints comprising;
a programmable precondition register that stores a set of precondition codes, wherein the set of precondition codes is identical for each watchpoint in the set of watchpoints;
a programmable action register that stores a set of action codes, wherein the set of action codes is identical for each watchpoint in the set of watchpoints; and
a first comparator, having inputs coupled to the precondition register, that compares at least one precondition code in the set of precondition codes with a first data value in the computer system and provides a signal to the action register in response thereto. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A computer system, comprising:
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at least one central processing unit;
a memory unit coupled to the at least one central processing unit;
a set of watchpoints defined in the computer system, each watchpoint in the set of watchpoints comprising;
a first programmable storage means for storing at least one precondition code that is identical for each watchpoint in the set of watchpoints;
a second programmable storage means for storing at least one action code that is identical for each watchpoint in the set of watchpoints; and
a comparator, having inputs responsive to the first programmable storage means, that compares the at least one precondition code with a data value in the computer system and provides a signal to the second programmable storage means in response thereto.
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16. A method of triggering a watchpoint in a computer system comprising at least one central processing unit and a memory unit coupled to the at least one central processing unit, the method comprising the steps of:
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defining a set of watchpoints in the computer system by defining a set of precondition registers and a set of action registers;
storing a set of precondition codes in a precondition register, wherein the set of precondition codes is identical for each watchpoint in the set of watchpoints;
storing a set of action codes in an action register, wherein the set of action codes is identical for each watchpoint in the set of watchpoints;
comparing at least one precondition code in the set of precondition codes with a first data value in the computer system and providing a signal to the action register in response thereto. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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Specification