Prototype development system

• US 6,502,221 B1
• Filed: 07/12/1999
• Issued: 12/31/2002
• Est. Priority Date: 07/14/1998
• Status: Expired due to Term

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Hasslen, Robert J. III, Nicolino, Sam J. Jr., Vogel, Ernest P., Martinez, Fernando G.
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Whitmore, Stacy
• Application Number:
  US09/351,783
• Time in Patent Office: 1,268 Days
• Field of Search: 295/07, 703/23.15, 716/16, 716/17, 716/1, 716/8, 716/4, 174/261, 705/28, 714/35, 361/600, 361/767, 361/769, 439/70, 439/912
• US Class Current: 716/137
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3308 using simulation
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H05K 1/029 having a programmable lay-out, i.e. adapted for choosing between a few possibilities
• CPC Class Codes: H05K 1/14 Structural association of two or more printed circuits providing electric connection to or between printed circuits H05K1/11, H01R12/00
• CPC Class Codes: H05K 1/148 Arrangements of two or more hingeably connected rigid printed circuit boards, i.e. connected by flexible means
• CPC Class Codes: H05K 3/0005 for designing circuits by computer
• CPC Class Codes: Y10T 29/49126 Assembling bases
• CPC Class Codes: Y10T 29/49208 by assembling plural parts

Abstract

A prototype development apparatus includes a logic board (LB) including a plurality of integrated circuit (IC) sites each adapted to receive an IC, logic traces coupled to each of the IC sites, and a plurality of logic board connector sites (LBCSs) configured to provide access to a number of the logic traces and each adapted to receive a connector. Additionally, a mezzanine board (MB) has a plurality of mezzanine board connector sites (MBCSs) each adapted to receive a connector and configured to provide access to a number of mezzanine traces interconnecting the LBCSs. The MB board is coupled to the LB and a portion of the logic traces are coupled to a portion of the mezzanine traces. In another embodiment the MB does not have any active components. This is because in this embodiment, the MB is configured to connect the pins of the connector sites according to a predetermined program. A method of prototyping a target circuit generates a netlist representative of the target circuit, divides the netlist into portions to be programmed into ICs on the LB and portions to be fabricated on the MB, such that the target circuit is configured from both the LB and the MB. Advantages of the present invention include providing a cost-effective technique for developing a prototype that combines the advantages of the custom prototype speed with the flexibility of the re-programmable emulators.

Claims

1. A prototype development apparatus comprising:

a logic board (LB) including a plurality of integrated circuit (IC) sites each adapted to receive an IC, logic traces coupled to each of said IC sites, and a plurality of logic board connector sites (LBCSs) each adapted to receive a connector and coupled to a number of said logic traces; and

a mezzanine board (MB) including a plurality of mezzanine board connector sites (MBCSs) each adapted to receive a connector and coupled to a number of mezzanine traces interconnecting said MBCSs;

said LBCSs each including a plurality of pads each coupled to a logic trace;

said LBCSs each including a pair of holes in said LB adjacent to said pads;

said MBCSs each including a plurality of pads each coupled to a mezzanine trace;

said MBCSs each including a pair of holes in said LB adjacent to said pads;

wherein each of said connectors includes;

a flexible printed circuit board having a plurality of traces with raised dots on a first side adapted to connect to a plurality of pads and raised dots on a second side adapted to connect to a plurality of pads;

a first pair of threaded receptors configured to receive a pair of threaded bolts disposed through said pair of holes in said LB, and configured such that when said threaded bolts are tightened, to press said dots on said first side to said plurality of pads in said LBCS; and

a second pair of threaded receptors configured to receive a pair of threaded bolts disposed through said pair of holes in said MB, and configured such that when said threaded bolts are tightened, to press dots on said second side to said plurality of pads in said MBCS.

5. The prototype development apparatus of claim 1, wherein:

each of said connectors further includes a resilient backing disposed behind said flexible printed circuit board to press said dots on said first side to said plurality of pads in said LBCS and to press said dots on said second side to said plurality of dotted pads in said MBCS.

7. The prototype development apparatus of claim 1, wherein:

each of said connectors has a connect density greater than about 100 dots/inch².

2. A prototype development apparatus comprising:

a logic board (LB) including a plurality of integrated circuit (IC) sites each adapted to receive an IC, logic traces coupled to each of said IC sites, and a plurality of logic board connector sites (LBCSs) each adapted to receive a connector and coupled to a number of said logic traces; and

a mezzanine board (MB) including a plurality of mezzanine board connector sites (MBCSs) each adapted to receive a connector and coupled to a number of mezzanine traces interconnecting said MBCSs;

said LBCSs each including a plurality of pads disposed in a substantially rectangular pattern each coupled to a logic trace;

said LBCSs each including a pair of holes in said LB adjacent to opposite sides of said rectangular pattern;

said MBCSs each including a plurality of pads disposed in a substantially rectangular pattern each coupled to a mezzanine trace;

said MBCSs each including a pair of holes in said LB adjacent to opposite sides of said rectangular pattern;

wherein each of said connectors includes;

a flexible printed circuit board having a plurality of traces with raised dots on a first side adapted to connect to a plurality of pads and raised dots on a second side adapted to connect to a plurality of pads;

of threaded bolts disposed through said pair of holes in said LB, and configured such that when said threaded bolts are tightened, to press said dots on said first side to said plurality of pads in said LBCS; and

a second pair of threaded receptors configured to receive a pair of threaded bolts disposed through said pair of holes in said MB, and configured such that when said threaded bolts are tightened, to press dots on said second side to said plurality of pads in said MBCS.

3. A prototype development apparatus comprising:

a logic board (LB) including a plurality of integrated circuit (IC) sites each adapted to receive an IC, logic traces coupled to each of said IC sites, and a plurality of logic board connector sites (LBCSs) each adapted to receive a connector and coupled to a number of said logic traces; and

a mezzanine board (MB) including a plurality of mezzanine board connector sites (MBCSs) each adapted to receive a connector and coupled to a number of mezzanine traces interconnecting said MBCSs;

said LBCSs each including a plurality of raised dots each coupled to a logic trace;

said LBCSs each including a pair of holes in said LB adjacent to said raised dots;

said MBCSs each including a plurality of raised dots each coupled to a mezzanine trace;

said MBCSs each including a pair of holes in said LB adjacent to said raised dots;

wherein each of said connectors includes;

a flexible printed circuit board having a plurality of connector traces exposed on a first side and adapted to connect to a plurality of dotted pads, and exposed on a second side and adapted to connect to a plurality of dotted pads;

a first pair of threaded receptors configured to receive a pair of threaded bolts disposed through said pair of holes in said LB, and configured such that when said threaded bolts are tightened, to press said connector traces exposed on said first side to said plurality of dotted pads in said LBCS; and

a second pair of threaded receptors configured to receive a pair of threaded bolts disposed through said pair of holes in said MB, and configured such that when said threaded bolts are tightened, to press said connector traces exposed on said second side to said plurality of dotted pads in said MBCS.

6. The prototype development apparatus of claim 3, wherein:

each of said connectors further includes a resilient backing disposed behind said flexible printed circuit board to press said connector traces exposed on said first side to said plurality of dotted pads in said LBCS and to press said connector traces exposed on said second side to said plurality of dotted pads in said MBCS.

8. The prototype development apparatus of claim 3, wherein:

each of said connectors has a connect density greater than about 100 dots/inch².

4. A prototype development apparatus comprising:

a logic board (LB) including a plurality of integrated circuit (IC) sites each adapted to receive an IC, logic traces coupled to each of said IC sites, and a plurality of logic board connector sites (LBCSs) each adapted to receive a connector and coupled to a number of said logic traces; and

a mezzanine board (MB) including a plurality of mezzanine board connector sites (MBCSs) each adapted to receive a connector and coupled to a number of mezzanine traces interconnecting said MBCSs;

said LBCSs each including a plurality of raised dots disposed in a substantially rectangular pattern each coupled to a logic trace;

said LBCSs each including a pair of holes in said LB adjacent to opposite sides of said rectangular pattern;

said MBCSs each including a plurality of raised dots disposed in a substantially rectangular pattern each coupled to a mezzanine trace;

said MBCSs each including a pair of holes in said LB adjacent to opposite sides of said rectangular pattern;

wherein each of said connectors includes;

a flexible printed circuit board having a plurality of connector traces exposed on a first side and adapted to connect to a plurality of dotted pads, and exposed on a second side and adapted to connect to a plurality of dotted pads;

a first pair, of threaded receptors configured to receive a pair of threaded bolts disposed through said pair of holes in said LB, and configured such that when said threaded bolts are tightened, to press said connector traces exposed on said first side to said plurality of dotted pads in said LBCS; and

a second pair of threaded receptors configured to receive a pair of threaded bolts disposed through said pair of holes in said MB, and configured such that when said threaded bolts are tightened, to press said connector traces exposed on said second side to said plurality of dotted pads in said MBCS.

9. A prototype development apparatus comprising:

a logic board (LB) including a plurality of integrated circuit (IC) sites each adapted to receive an IC, logic traces coupled to each of said IC sites, and a plurality of logic board connector sites (LBCSs) each adapted to receive a connector and coupled to a number of said logic traces; and

a mezzanine board (MB) including a plurality of mezzanine board connector sites (MBCSs) each adapted to receive a connector and coupled to a number of mezzanine traces interconnecting said MBCSs;

said logic traces being divided into a group of power traces, a group of clock traces and a group of signal traces;

said LBCSs being coupled to a number of signal traces;

said LB including a logic board clock connector site LBCCS coupled to a number of said clock traces and adapted to receive a clock connector;

said prototype development apparatus further comprising a clock mezzanine board (CMB) having a clock mezzanine board connector site (CMBCS) adapted to receive said clock connector and coupled to a number of mezzanine clock traces.

10. The prototype development apparatus of claim 9, wherein:

said LB includes a programmable delay buffer coupled to said clock traces and configured to selectively delay signals on said clock traces.

11. A prototype development apparatus comprising:

a logic board (LB) including a plurality of integrated circuit (IC) sites each adapted to receive an IC, logic traces coupled to each of said IC sites, and a plurality of logic board connector sites (LBCSs) each adapted to receive a connector and coupled to a number of said logic traces; and

a mezzanine board (MB) including a plurality of mezzanine board connector sites (MBCSs) each adapted to receive a connector and coupled to a number of mezzanine traces interconnecting said MBCSs;

said LB including a logic board incremental connector site LBICS coupled to a number of said logic traces and adapted to receive an incremental connector;

said prototype development apparatus further comprising an incremental mezzanine board (IMB) having an incremental mezzanine board connector site (IBMCS) adapted to receive said incremental connector and coupled to a number of incremental mezzanine traces.

12. A prototype development apparatus comprising:

a logic board (LB) including a plurality of integrated circuit (IC) sites each adapted to receive an IC, logic traces coupled to each of said IC sites, and a plurality of logic board connector sites (LBCSs) each adapted to receive a connector and coupled to a number of said logic traces; and

a mezzanine board (MB) including a plurality of mezzanine board connector sites (MBCSs) each adapted to receive a connector and coupled to a number of mezzanine traces interconnecting said MBCSs;

said ICs including programmable grid arrays (PGAs);

said LB including a logic board clock connector site LBCCS coupled to a number of said clock traces and adapted to receive a clock connector;

said prototype development apparatus further comprising a clock mezzanine board (CMB) having a clock mezzanine board connector site (CMBCS) adapted to receive said clock connector and coupled to a number of mezzanine clock traces;

said prototype development apparatus further comprising a buffer board disposed between said LB and said MB and having a plurality of buffer board connector sites (BBCSS) coupled to a number of buffer traces and adapted to receive a connector;

one of said BBCSs being coupled to said LB and another of said BBCSs being coupled to said MB.

13. A method of constructing a prototype apparatus comprising the steps of:

fabricating a logic board (LB) including a plurality of integrated circuit (IC)sites each adapted to receive an IC, logic traces coupled to each of said IC sites, and a plurality of logic board connector sites (LBCSs) each adapted to receive a connector and coupled to a number of said logic traces;

fabricating a mezzanine board (MB) having a plurality of mezzanine board connector sites (MBCSs) each adapted to receive a connector and coupled to a number of mezzanine traces interconnecting said MBCSs;

coupling said LB and said MB via a plurality of connectors connected to said LBCSs and said MBCSs;

fabricating a second mezzanine board (2 MB) having a plurality of second mezzanine board connector sites (2 MBCSs) each adapted to receive a connector and coupled to a number of mezzanine traces interconnecting said 2 MBCSs and having a different connectivity between said 2 MBCSs than said MBCSs;

decoupling said MB from said LB; and

coupling said LB and said 2 MB via a plurality of connectors connected to said LBCSs and said 2 MBCSs.

14. A method of constructing a prototype apparatus comprising the steps of:

fabricating a logic board (LB) including a plurality of integrated circuit (IC)sites each adapted to receive an IC, logic traces coupled to each of said IC sites, and a plurality of logic board connector sites (LBCSs) each adapted to receive a connector and coupled to a number of said logic traces;

fabricating a mezzanine board (MB) having a plurality of mezzanine board connector sites (MBCSs) each adapted to receive a connector and coupled to a number of mezzanine traces interconnecting said MBCSs; and

coupling said LB and said MB via a plurality of connectors connected to said LBCSs and said MBCSS;

fabricating a plurality of identical logic boards (LBs) each including a plurality of integrated circuit (IC) sites each adapted to receive an IC, logic traces coupled to each of said IC sites, and a plurality of logic board connector sites (LBCSs) coupled to a number of said logic traces and each adapted to receive a connector;

fabricating a plurality of different mezzanine boards (MBs) having a plurality of mezzanine board connector sites (MBCSs) each adapted to receive a connector and coupled to a number of differently routed mezzanine traces interconnecting said MBCSs; and

coupling each of said LBs and said MBs via a plurality of connectors connected to said LBCSs and said MBCSs.

15. A method of constructing a prototype apparatus comprising the steps of:

fabricating a logic board (LB) including a plurality of integrated circuit (IC)sites each adapted to receive an IC, logic traces coupled to each of said IC sites, and a plurality of logic board connector sites (LBCSs) each adapted to receive a connector and coupled to a number of said logic traces;

fabricating a mezzanine board (MB) having a plurality of mezzanine board connector sites (MBCSs) each adapted to receive a connector and coupled to a number of mezzanine traces interconnecting said MBCSs; and

coupling said LB and said MB via a plurality of connectors connected to said LBCSs and said MBCSs;

fabricating a plurality of identical logic boards (LBs) each including a plurality of integrated circuit (IC) sites each adapted to receive an IC, logic traces coupled to each of said IC sites, and a plurality of logic board connector sites (LBCSs) coupled to a number of said logic traces and each adapted to receive a connector;

fabricating a plurality of different mezzanine boards (MBs) having a plurality of mezzanine board connector sites (MBCSs) each adapted to receive a connector and coupled to a number of differently routed mezzanine traces interconnecting said;

MBCSs, said differently routed mezzanine traces being routed based on requirements of a target circuit; and

coupling each of said LBs and said MBs via a plurality of connectors connected to said LBCSs and said MBCSs.

16. A method of constructing a prototype apparatus comprising the steps of:

fabricating a logic board (LB) including a plurality of integrated circuit (IC)sites each adapted to receive an IC, logic traces coupled to each of said IC sites, and a plurality of logic board connector sites (LBCSs) each adapted to receive a connector and coupled to a number of said logic traces;

fabricating a mezzanine board (MB) having a plurality of mezzanine board connector sites (MBCSs) each adapted to receive a connector and coupled to a number of mezzanine traces interconnecting said MBCSs; and

coupling said LB and said MB via a plurality of connectors connected to said LBCSs and said MBCSs;

fabricating a plurality of identical logic boards (LBs) each including a plurality of integrated circuit (IC) sites each adapted to receive an IC, logic traces coupled to each of said IC sites, and a plurality of logic board connector sites (LBCSs) coupled to a number of said logic traces and each adapted to receive a connector;

partially fabricating a plurality of identical mezzanine boards (MBs) having a plurality of mezzanine board connector sites (MBCSs) each adapted to receive a connector and coupled to a number of identically routed mezzanine traces interconnecting said MBCSs; and

completing fabricating of said plurality of said identical MBs by routing differently routed mezzanine traces on each of said MBs, said differently routed mezzanine traces being routed based on requirements of a target circuit.

17. A method of prototyping a target circuit using a logic board (LB) having a plurality of programmable integrated circuits (PICs) and a number of logic traces, and a mezzanine board (MB), comprising the steps of:

generating a net list representative of said target circuit;

dividing said net list into first portions to be programmed into said PICs and second portions to interconnect said PICs;

programming said first portions into said PICs;

fabricating said MB including mezzanine traces based on said second portions; and

coupling said logic traces and said mezzanine traces such that said target circuit is configured from both said LB and said MB;

wherein said LB has a clock mezzanine board (CMB) coupled to provide a clock to said PICs, and wherein said method further comprises the steps of;

supplying a clock to said PICs on said LB.

18. A method of prototyping a target circuit using a logic board (LB) having a plurality of programmable integrated circuits (PICs) and a number of logic traces, and a mezzanine board (MB), comprising the steps of:

generating a net list representative of said target circuit;

dividing said net list into first portions to be programmed into said PICs and second portions to interconnect said PICs;

programming said first portions into said PICs;

fabricating said MB including mezzanine traces based on said second portions; and

coupling said logic traces and said mezzanine traces such that said target circuit is configured from both said LB and said MB;

wherein;

a plurality of said mezzanine traces are spare traces; and

when an error is discovered and corrected to create a new target circuit, said method further comprises the steps of;

regenerating a new netlist representative of said new target circuit;

dividing said new netlist into new first portions to be programmed into said PICs and new second portions to interconnect said PICs, said dividing step using said spare traces to form a part of said second portion;

programming said new first portions into said PICs; and

coupling said logic traces and said mezzanine traces such that said target circuit is configured from both said LB and said MB.