Flash memory cell with contactless bit line, and process of fabrication

• US 6,503,785 B2
• Filed: 05/21/2001
• Issued: 01/07/2003
• Est. Priority Date: 05/22/2000
• Status: Expired due to Term

• Current Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Original Assignee: Actrans Systems Inc. (Microchip Technology Incorporated)
• Inventors: Chen, Chiou-Feng
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Tran, Mai-Huong
• Application Number:
  US09/862,078
• Publication Number:
  US 20020008277A1
• Time in Patent Office: 596 Days
• Field of Search: 438/265, 438/267, 438/596, 257/314, 257/315, 257/316, 257/319, 257/320
• US Class Current: 438/211
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND

Abstract

Memory cell array and process of fabrication in which a floating gate is formed on a substrate for each of a plurality of memory cells, a control gate is formed above and in vertical alignment with each of the floating gates, source regions are formed in the substrate between and partially overlapped by first edge portions of the floating gates in adjacent ones of the cells, bit lines are formed in the substrate midway between second edge portions of the floating gates in adjacent ones of the cells, and a select gate is formed across the control gates, the floating gates, the bit lines and the source regions.

Claims

1. In a process of fabricating a memory cell array, the steps of:

forming a floating gate on a substrate for each of a plurality of memory cells positioned side-by-side on the substrate, forming a control gate in overlying relationship with each of the floating gates, forming source regions in the substrate between and partially overlapped by first edge portions of the floating gates in adjacent ones of the cells, forming bit lines in the substrate midway between second edge portions of the floating gates in adjacent ones of the cells, and forming a select gate which crosses over the control gates, the floating gates, the bit lines and the source regions.

2. The process of claim 1 wherein electron tunneling paths are formed between the first edge portions of the floating gates and portions of the source regions which are overlapped by the first edge portions.

3. The process of claim 1 wherein the bit lines are positioned midway between the second edge portions of the floating gates.

4. The process of claim 1 wherein the bit lines are positioned beneath the select gate, and two select gates transistors are formed using one of the bit lines and the select gate.

5. The process of claim 1 including the step of applying a negative voltage to the control gates of unselected memory cells to turn off the floating gate transistors in those cells during program and read operations.

6. In a process of fabricating a memory cell array, the steps of:

forming a floating gate on a substrate for each of a plurality of memory cells positioned side-by-side on the substrate, forming a control gate in overlying relationship with each of the floating gates being formed to be wider than the control gates and to have first and second edge portions which project laterally beyond the edges of the control gates, forming source regions in the substrate between and partially overlapped by first edge portions of the floating gates in adjacent ones of the cells, forming bit lines in the substrate midway between second edge portions of the floating gates in adjacent ones of the cells, and forming a select gate which crosses over the control gates, the floating gates, the bit lines and the source regions.

7. The process of claim 6 wherein the laterally projecting edge portions of the floating gates are formed to be sharply rounded.

8. The process of claim 7 wherein the select gates are formed with side walls which face the sharply rounded lateral edges of the floating gates, and electron tunneling paths are formed between the sharply rounded lateral edge portions of the floating gates and the side walls of the select gates.

9. In a process of fabricating a memory cell array, the steps of:

forming a floating gate on a substrate for each of a plurality of memory cells positioned side-by-side on the substrate, forming a control gate in overlying relationship with each of the floating gates, forming source regions in the substrate between and partially overlapped by first edge portions of the floating gates in adjacent ones of the cells, forming bit lines in the substrate midway between second edge portions of the floating gates in adjacent ones of the cells, forming a select gate which crosses over the control gates, the floating gates, the bit lines and the source regions, and forming a hot carrier path for the injection of electrons during a program operation from a mid-channel region in the substrate between the select gate and the floating gate, to the floating gate, with high voltage coupling between the control gate and the floating gate.

10. In a process of fabricating a memory cell, the steps of:

forming a first layer of oxide on a substrate, forming a poly-1 layer on the first oxide layer, forming a dielectric film over the poly-1 layer, forming a poly-2 layer over the dielectric film, forming a dielectric film over the poly-2 layer, etching away portions of the poly-2 layer and the dielectric film to form control gates, forming oxide spacers around the control gates, forming source and bit line diffusion regions in the substrate using the dielectric spacers as a mask, removing the dielectric spacers, forming a dielectric layer around the control gates, enlarging the source diffusion regions using the dielectric layer around the control gates as a mask, etching the poly-1 layer using the dielectric layer around the control gates as a mask to form floating gates which are wider than the control gate and have edge portions which project laterally from the edges of the control gates, building up oxide on the side walls of the floating gates, around the control gates and on the substrate above the source and bit line diffusion regions, depositing a poly-3 layer over the built-up oxide, and etching away portions the poly-3 layer to form select gates which overlie the floating and control gates, the bit line diffusion regions and the source diffusion regions.

11. The process of claim 10 wherein oxide is built up by thermal oxidation which produces a sharply curved rounding of the laterally projecting edges of the floating gates.

12. In a process of fabricating an array of memory cells positioned side-by-side on a substrate, the steps of:

forming a floating gate and a control gate for each of the memory cells, with the control gate overlying the floating gate and the floating gates being wider and substantially thinner than the control gates and having first and second sharply rounded edge portions which project laterally beyond the edges of the control gates, forming source regions in the substrate between and partially overlapped by the first edge portions of the floating gates in adjacent ones of the cells, forming bit lines in the substrate between the second edge portions of the floating gates in adjacent ones of the cells, and forming a select gate which crosses over the control gates, the floating gates, the bit lines and the source regions.

13. The process of claim 12 wherein the floating gate is formed with a thickness on the order of 100-1000 Å

, and the control gate is formed with a thickness on the order of 1500-3500 Å

.

14. The process of claim 12 wherein the bit lines are positioned midway between the second edge portions of the floating gates.

15. In a process of fabricating a memory cell array having a plurality of memory cells positioned side-by-side on a substrate, the steps of:

forming a floating gate and a control gate for each of the memory cells, with the control gate overlying the floating gate, forming source regions in the substrate between and partially overlapped by the first edge portions of the floating gates in adjacent ones of the cells, forming bit lines in the substrate midway between the second edge portions of the floating gates in adjacent ones of the cells, forming a select gate which crosses over the control gates, the floating gates, the bit lines and the source regions, and providing dielectric material between the floating gate and the control gate and between the control gate and the select gate, with the dielectric material between the floating gate and the control gate being substantially thinner than the dielectric material between the control gate and the select gate.

16. The process of claim 15 wherein the dielectric material between the floating gate and the control gate is formed to have a thickness on the order of 120 Å

-500 Å

, and the dielectric material between the control gate and the select gate is formed to have a thickness on the order of 1000 Å

-3000 Å

.

17. The process of claim 15 wherein the bit lines are positioned midway between the second edge portions of the floating gates.