Power MOS device with asymmetrical channel structure for enhanced linear operation capability

• US 6,503,786 B2
• Filed: 08/08/2001
• Issued: 01/07/2003
• Est. Priority Date: 08/08/2000
• Status: Expired due to Term

• Current Assignee: Microsemi Corporation (Microchip Technology Incorporated)
• Original Assignee: Advanced Power Technology Incorporated (Microchip Technology Incorporated)
• Inventors: Klodzinski, Stanley J.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): PHAM, HOAI V
• Application Number:
  US09/925,289
• Publication Number:
  US 20020020873A1
• Time in Patent Office: 517 Days
• Field of Search: 257/341, 257/345, 257/391, 257/403, 257/404, 438/173, 438/174, 438/192, 438/194, 438/206, 438/209, 438/212, 438/217, 438/223, 438/286, 438/289
• US Class Current: 438/212
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

A power MOSFET type device, which can include an IGBT or other VDMOS device having similar forward transfer characteristics, is formed with an asymmetrical channel, to produce different gate threshold voltage characteristics in different parts of the device. The different gate threshold voltage characteristics can be achieved either by different source region doping concentrations or different body region doping concentrations subjacent the gate oxide, or by asymmetrical gate oxide thicknesses. The portion of overall channel affected can be 50% or such other proportion as the designer chooses, to reduce the zero temperature coefficient point of the device and improve its Safe Operating Area in linear operation, while retaining low conduction loss. Multiple power MOSFET devices with asymmetrical channels can easily be used safely in parallel linear power amplifier circuits.

Claims

1. A method of making a power MOSFET type device for stable linear operation, comprising:

providing a substrate including an active device region of a first dopant type;

forming a body region of a second dopant type opposite the first dopant type adjacent a surface of the substrate;

forming first and second source regions of the first dopant type within the body region, positioned to define separate channel regions in the body region adjacent the surface of the substrate;

forming a gate structure including first and second gate portions on the substrate surface respectively overlying the first and second channel regions;

adjusting a gate threshold voltage characteristic of each of the channel regions to produce an asymmetric gate threshold voltage characteristic in the device.

2. A method according to claim 1 including adjusting the gate threshold voltage characteristic of the entire first channel region relative to the gate threshold voltage characteristic of the second channel region to produce a 50% asymmetric device.

3. A method according to claim 1 including adjusting the gate threshold voltage characteristic of less than the entire first channel region relative to the gate threshold voltage characteristic of the second channel region to produce an asymmetric device in which unequal portions of the overall channel have different gate threshold voltage characteristics.

4. A method according to claim 1 including adjusting the gate threshold voltage characteristic of the first channel region relative to the gate threshold voltage characteristic of the second channel region to reduce zero temperature coefficient point (ZTCP) relative to a device having a single gate threshold voltage characteristic.

5. A method according to claim 1 including adjusting the gate threshold voltage characteristic of the first channel region relative to the gate threshold voltage characteristic of the second channel region to reduce variation in transconductance of the device as a function of temperature relative to a device having a single gate threshold voltage characteristic.

6. A method according to claim 1 including adjusting the relative gate threshold voltage characteristics of portions of the first and second channel regions to produce a conduction characteristic below the zero temperature coefficient point (ZTCP) which has a reduced variation with temperature relative to the conduction characteristic of a device having a single gate threshold voltage characteristic.

7. A method according to claim 1 in which adjusting a gate threshold voltage characteristic of each of the channel regions includes differentially doping the first and second channel regions so that the first channel region has a doping concentration less than a doping concentration of the second channel region.

8. A method according to claim 1 in which adjusting a gate threshold voltage characteristic of each of the channel regions includes differentially doping the first and second source regions so that the first source region has a doping concentration greater than a doping concentration of the second source region.

9. A method according to claim 1 in which adjusting a gate threshold voltage characteristic of each of the channel regions includes varying the thicknesses of a gate dielectric layer of the gate structures so that the dielectric layer of the first gate structure has a thickness less than a thickness of the dielectric of the second gate structure.

10. A method of making a vertical double-diffused power MOSFET type device for stable linear operation, comprising:

providing a substrate including an active device region of a first dopant type forming a vertical drain region;

forming a body region of a second dopant type opposite the first dopant type adjacent a surface of the substrate bounded on opposite sides by the vertical drain region;

forming first and second source regions of the first dopant type within the body region, positioned to define separate channel regions in the body region adjacent the surface of the substrate, each channel region extending to the vertical drain region on opposite sides of the body region;

forming a gate structure including first and second gate portions on the substrate surface respectively overlying the first and second channel regions;

adjusting a gate threshold voltage characteristic of each of the channel regions to produce an asymmetric gate threshold voltage characteristic in the device.

11. A method according to claim 10 including adjusting the relative gate threshold voltage characteristics of portions of the first and second channel regions to produce a conduction characteristic below the zero temperature coefficient point (ZTCP) which has a reduced variation with temperature relative to the conduction characteristic of a device having a single gate threshold voltage characteristic.