Semiconductor device and method for manufacturing the same

• US 6,503,826 B1
• Filed: 03/16/2000
• Issued: 01/07/2003
• Est. Priority Date: 11/12/1997
• Status: Expired due to Fees

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Oda, Noriaki
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): ISAAC, STANETTA D
• Application Number:
  US09/527,212
• Time in Patent Office: 1,027 Days
• Field of Search: 438/301, 438/618, 438/624
• US Class Current: 438/624
• CPC Class Codes: H01L 21/02129 the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/3145 formed by deposition from a gas or vapour
• CPC Class Codes: H01L 21/31612 on a silicon body
• CPC Class Codes: H01L 21/31625 Deposition of boron or phosphorus doped silicon oxide, e.g. BSG, PSG, BPSG
• CPC Class Codes: H01L 21/3185 of siliconnitrides
• CPC Class Codes: H01L 23/564 Details not otherwise provided for, e.g. protection against moisture getters H01L23/26
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

In an LDD structure MOSFET, a protecting multilayer insulating film is formed to cover a gate electrode in order to protect the gate electrode and the gate oxide film from a moisture included in an upper level layer. The protecting multilayer insulating film includes a protecting nitride film for preventing infiltration of moisture, and another protecting insulator film having a compressive stress for relaxing a tensile stress of the protecting nitride film. Thus, it is possible to prevent infiltration of moisture, and simultaneously, it is possible to minimize energy levels for trapping electrons and holes, which would have otherwise been formed within the gate oxide film and at a boundary between the gate oxide film and the semiconductor substrate because of the tensile stress of the protecting nitride film.

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of:

forming a first insulator film on a semiconductor substrate of a first conductivity type to define a device region;

forming a gate insulator film on said semiconductor substrate within said device region;

forming a gate electrode on said gate insulator film within said device region;

forming a source region and a drain region of a second conductivity type opposite to said first conductivity type in said semiconductor substrate within said device region in self-alignment by using said gate electrode as a mask;

forming a sidewall insulator film on a side wall of said gate electrode;

forming a source lead-out region and a drain lead-out region of said second conductivity type in said semiconductor substrate within said device region in self-alignment by using said sidewall insulator film and said gate electrode as a mask;

forming a protecting insulating film having at least one insulator film on the whole surface of said semiconductor substrate including said gate electrode and said sidewall insulator film; and

forming an interlayer insulator film on the whole surface of said semiconductor substrate including said protecting insulating film for isolating said gate electrode from a metal interconnection formed on said interlayer insulator film,

wherein the step of forming said protecting insulating film includes the steps of depositing a first oxide film having a thickness of 90 nm to 110 nm on the whole surface of said semiconductor substrate including said gate electrode and said sidewall insulator film by an atmospheric pressure chemical vapor deposition process,

succeedingly depositing a nitride film having a thickness of 10 nm to 20 nm by a thermal chemical vapor deposition process, and

thereafter, depositing a second oxide film having a thickness of 40 nm to 60 nm by a plasma chemical vapor deposition process.

2. A method for manufacturing a semiconductor device claimed in claim 1 wherein said thermal chemical vapor deposition is conducted at a temperature of 700°

C., said atmospheric pressure chemical vapor deposition process is conducted at a temperature of 400°

C., and said plasma chemical vapor deposition process is conducted at a temperature range of 250°

C. to 300°

C.

3. A method for manufacturing a semiconductor device claimed in claim 1 wherein before said first nitride film having the thickness of 10 nm to 20 nm is deposited by the thermal chemical vapor deposition process, said semiconductor substrate is heat-treated in a deposition machine for depositing said first nitride film, for not less than ten seconds at a temperature of not less than 700°

C. and a gas pressure of not greater than 10<sup>−

3</sup> Torr.

4. A method for manufacturing a semiconductor device, comprising the steps of:

forming a first insulator film on a semiconductor substrate of a first conductivity type to define a device region;

forming a gate insulator film on said semiconductor substrate within said device region;

forming a gate electrode on said gate insulator film within said device region;

forming a source region and a drain region of a second conductivity type opposite to said first conductivity type in said semiconductor substrate within said device region in self-alignment by using said gate electrode as a mask;

forming a sidewall insulator film on a side wall of said gate electrode;

forming a source lead-out region and a drain lead-out region of said second conductivity type in said semiconductor substrate within said device region in self-alignment by using said sidewall insulator film and said gate electrode as a mask;

forming a protecting insulating film having at least one insulator film on the whole surface of said semiconductor substrate including said gate electrode and said sidewall insulator film; and

forming an interlayer insulator film on the whole surface of said semiconductor substrate including said protecting insulating film for isolating said gate electrode from a metal interconnection formed on said interlayer insulator film,

wherein the step of forming said protecting insulating film includes the steps of depositing a first nitride film having a thickness of 10 nm to 20 nm by a thermal chemical vapor deposition process, and succeedingly depositing a second nitride film having a thickness of 30 nm to 100 nm by a plasma chemical vapor deposition process.

5. A method for manufacturing a semiconductor device claimed in claim 4 wherein said thermal chemical vapor deposition is conducted at a temperature of 700°

C., and said plasma chemical vapor deposition process is conducted at a temperature range of 250°

C. to 300°

C.

6. A method for manufacturing a semiconductor device claimed in claim 4 wherein before said first nitride film having the thickness of 10 nm to 20 nm is deposited by the thermal chemical vapor deposition process, said semiconductor substrate is heat-treated in a deposition machine for depositing said first nitride film, for not less than ten seconds at a temperature of not less than 700°

C. and a gas pressure of not greater than 10<sup>−

3</sup> Torr.

7. A method for manufacturing a semiconductor device, comprising the steps of:

forming a first insulator film on a semiconductor substrate of a first conductivity type to define a device region;

forming a gate insulator film on said semiconductor substrate within said device region;

forming a gate electrode on said gate insulator film within said device region;

forming a source region and a drain region of a second conductivity type opposite to said first conductivity type in said semiconductor substrate within said device region in self-alignment by using said gate electrode as a mask;

forming a sidewall insulator film on a side wall of said gate electrode;

forming a source lead-out region and a drain lead-out region of said second conductivity type in said semiconductor substrate within said device region in self-alignment by using said sidewall insulator film and said gate electrode as a mask;

forming a protecting insulating film having at least one insulator film on the whole surface of said semiconductor substrate including said gate electrode and said sidewall insulator film; and

forming an interlayer insulator film on the whole surface of said semiconductor substrate including said protecting insulating film for isolating said gate electrode from a metal interconnection formed on said interlayer insulator film,

wherein the steps of forming said protecting insulating film includes the step of depositing an oxide film having a thickness of 90 nm to 110 nm on the whole surface of said semiconductor substrate including said gate electrode and said sidewall insulator film by an atmospheric pressure chemical vapor deposition process,

succeedingly depositing a first nitride film having a thickness of 10 nm to 20 nm by a thermal chemical vapor deposition process, and

thereafter, depositing a second nitride film having a thickness of 30 nm to 100 nm by a plasma chemical vapor deposition process.

8. A method for manufacturing a semiconductor device claimed in claim 7 wherein said thermal chemical vapor deposition is conducted at a temperature of 700°

C., said atmospheric pressure chemical vapor deposition process is conducted at a temperature of 400°

C., and said plasma chemical vapor deposition process is conducted at a temperature range of 250°

C. to 300°

C.

9. A method for manufacturing a semiconductor device claimed in claim 7 wherein before said first nitride film having the thickness of 10 nm to 20 nm is deposited by the thermal chemical vapor deposition process, said semiconductor substrate is heat-treated in a deposition machine for depositing said first nitride film, for not less than ten seconds at a temperature of not less than 700°

C. and a gas pressure of not greater than 10<sup>−

3</sup> Torr.