Field effect transistor and method of manufacturing the same

• US 6,504,176 B2
• Filed: 04/03/2001
• Issued: 01/07/2003
• Est. Priority Date: 04/06/2000
• Status: Expired due to Term

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Kitabatake, Makoto, Yokogawa, Toshiya, Uchida, Masao, Kusumoto, Osamu, Takahashi, Kunimasa
• Primary Examiner(s): Lee, Eddie
• Assistant Examiner(s): Lee, Eugene
• Application Number:
  US09/824,922
• Publication Number:
  US 20010038108A1
• Time in Patent Office: 644 Days
• Field of Search: 257/77, 257/328, 257/330, 257/329, 257/332, 257/288, 438/105, 438/931
• US Class Current: 257/77
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

There are provided a field effect transistor with a high withstand voltage and low loss and a method of manufacturing the same. The field effect transistor includes an n-type substrate, an n-type semiconductor layer formed on the n-type substrate, a p-type semiconductor layer formed on the n-type semiconductor layer, a p-type region embedded in the n-type semiconductor layer, an n-type region embedded in the n-type semiconductor layer and the p-type semiconductor layer, an n-type source region disposed in the p-type semiconductor layer on its surface side, an insulating layer disposed on the p-type semiconductor layer, a gate electrode disposed on the insulating layer, a source electrode, and a drain electrode. The n-type semiconductor layer, the p-type semiconductor layer, and the p-type region are made of wide-gap semiconductors with a bandgap of at least 2 eV, respectively.

Claims

1. A field effect transistor, comprising:

an n-type semiconductor layer;

a p-type semiconductor layer formed on the n-type semiconductor layer;

a p-type region embedded in the n-type semiconductor layer to be in contact with the p-type semiconductor layer;

a drain electrode electrically connected to the n-type semiconductor layer;

an n-type source region disposed in contact with the p-type semiconductor layer;

an n-type region passing through the p-type semiconductor layer to reach the n-type semiconductor layer;

an insulating layer disposed adjacent to the p-type semiconductor layer; and

a gate electrode disposed on the insulating layer,

wherein the n-type semiconductor layer, the p-type semiconductor layer, and the p-type region respectively are made of wide-gap semiconductors with a bandgap of at least 2 eV;

a depletion region is formed so as to completely block an electron conduction path during an off state;

the n-type source region is disposed in a surface portion of the p-type semiconductor layer and around the n-type region, and a portion of the n-type source region other than its surface is surrounded by the p-type semiconductor layer,

the gate electrode is disposed in a place corresponding to that of a portion of the p-type semiconductor layer between the n-type region and the n-type source region with the insulating layer interposed between the gate electrode and the portion of the p-type semiconductor layer, and

the p-type region is disposed around the n-type region.

2. The field effect transistor according to claim 1, wherein the wide-gap semiconductor is SiC.

3. The field effect transistor according to claim 2, further comprising a substrate made of SiC,

wherein the n-type semiconductor layer is formed on the substrate, and the substrate is a β -SiC(100) substrate, a β

-SiC(110) substrate, a 6H α

-SiC(1-100) substrate, a 4H α

-SiC(1-100) substrate, an α

-SiC(11-20) substrate, or one of substrates with planes obtained by off-cutting of planes thereof by a tilt angle within 15 degrees, or is one of the following substrates with a Si plane;

a β

-SiC(111) substrate, a 6H α

-SiC(0001) substrate, a 4H α

-SiC(0001) substrate, a 15R-SiC substrate, and substrates with planes obtained by off-cutting of the Si planes thereof by a tilt angle within 10 degrees.

4. The field effect transistor according to claim 1, further comprising a trench passing through the p-type semiconductor layer to reach the n-type semiconductor layer,

wherein the insulating layer is disposed on at least a side wall of the trench,

the n-type source region is disposed in a surface portion of the p-type semiconductor layer and around the insulating layer, and

the p-type region is disposed around the trench.

5. The field effect transistor according to claim 4, wherein the insulating layer disposed on the side wall has a mean thickness not exceeding 500 nm.

6. The field effect transistor according to claim 1, wherein a total of a mean thickness of the n-type semiconductor layer and a mean thickness of the p-type semiconductor layer does not exceed 20 μ

m.

7. The field effect transistor according to claim 1, wherein the p-type region has a depth not exceeding 10 μ

m.

8. A field effect transistor, comprising:

an n-type semiconductor layer;

a p-type semiconductor layer formed on the n-type semiconductor layer;

a p-type region embedded in the n-type semiconductor layer to be in contact with the p-type semiconductor layer;

a drain electrode electrically connected to the n-type semiconductor layer;

an n-type source region disposed in contact with the p-type semiconductor layer;

an insulating layer disposed adjacent to the p-type semiconductor layer;

a gate electrode disposed on the insulating layer, and

an n-type region passing through the p-type semiconductor layer to reach the n-type semiconductor layer,

wherein the n-type semiconductor layer, the p-type semiconductor layer, and the p-type region respectively are made of wide-gap semiconductors with a bandgap of at least 2 eV,

the n-type source region is disposed in a surface portion of the p-type semiconductor layer and around the n-type region, and a portion of the n-type source region other than its surface is surrounded by the p-type semiconductor layer,

the gate electrode is disposed in a place corresponding to that of a portion of the p-type semiconductor layer between the n-type region and the n-type source region with the insulating layer interposed between the gate electrode and the portion of the p-type semiconductor layer, and

the p-type region is disposed around the n-type region.