Indirect back surface contact to semiconductor devices

• US 6,504,178 B2
• Filed: 04/05/2001
• Issued: 01/07/2003
• Est. Priority Date: 07/02/1999
• Status: Expired due to Term

• Current Assignee: Digirad Corporation
• Original Assignee: Digirad Corporation
• Inventors: Wilson, Richard, Carlson, Lars S., Zhao, Shulai
• Primary Examiner(s): Flynn, Nathan J.
• Assistant Examiner(s): FORDE, REMMON R
• Application Number:
  US09/828,694
• Publication Number:
  US 20020011639A1
• Time in Patent Office: 642 Days
• Field of Search: 257/86, 257/87, 257/88, 257/106, 257/46, 257/601, 257/656, 257/605, 257/749
• US Class Current: 257/86
• CPC Class Codes: H01L 27/146 Imager structures
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures

Abstract

A semiconductor imaging device is disclosed. The device includes a substrate having at least first and second surfaces opposing each other, and a circuit layer. The substrate is doped to exhibit a first conductivity type. The substrate includes a conducting layer, a region, and a plurality of doped regions. The conducting layer includes a first type dopants incorporated near the first surface. The region includes a heavily doped area within the substrate near the second surface. The plurality of doped regions includes a second type dopants formed on the second surface. The circuit layer is formed over the second surface to provide gate contacts to and readout circuits for the plurality of doped regions. The readout circuit provides readout of optical signals from pixels.

Claims

1. A semiconductor imaging device, comprising:

a substrate having at least first and second surfaces opposing each other, and doped to exhibit a first conductivity type, said substrate including;

a bias electrode layer of the first conductivity type formed internal to the substrate, near the first surface,

a region of the first conductivity type heavily doped over the second surface, said region configured to provide contact to the first surface from the second surface, and

a plurality of doped regions of a second conductivity type on the second surface; and

a circuit layer formed over the second surface to provide gate contacts to and readout circuits for said plurality of doped regions, such that the readout circuits provide electrical outputs related to the optical signals detected by pixels.

2. The device of claim 1, further comprising:

a guard ring formed between said region of the first conductivity type and said plurality of doped regions of the second conductivity type, said guard ring configured to isolate said region of the first conductivity type from the pixels.

3. The device of claim 2, wherein said region of the first conductivity type reduces leakage current of said guard ring.

4. The device of claim 1, wherein said first and second conductivity type is caused by n-type dopants and p-type dopants, respectively.

5. The device of claim 1, wherein said substrate includes silicon.

6. The device of claim 1, wherein said bias electrode layer is coated with one or more transparent layers to provide an external transparent contact layer, anti-reflective coating, or both an external transparent contact layer and a anti-reflective coating.

7. The device of claim 6, wherein said transparent layers include one or more insulating dielectric layers.

8. The device of claim 7, wherein said dielectric layers include one or more of titanium dioxide (TiO₂), aluminum oxide (Al₂O₃), zirconium dioxide (ZrO₂) zinc sulfide (ZnS), or silicon dioxide (SiO₂).

9. The device of claim 1, wherein said substrate further includes junction regions between the plurality of doped regions of the second conductivity type and the bias electrode layer of the first conductivity type.

10. The device of claim 9, wherein said junction regions are fully depleted to allow photon sensing from the first surface.

11. The device of claim 1, wherein said region of the first conductivity type is a heavily doped n-type moat.

14. The array of claim 11, further comprising:

a plurality of metal contacts coupled to said plurality of regions to provide ohmic contacts.

15. The array of claim 11, wherein said substrate further includes junction regions between the plurality of regions and the conducting layer.

16. The array of claim 15, wherein said junction regions are fully depleted to allow photon sensing from a surface opposite said conducting layer.

12. A photodiode array, comprising:

a substrate with at least two surfaces opposing each other, said substrate formed with a first type dopants;

a conducting layer of a first conductivity type within the substrate near one of said at least two surfaces of said substrate;

a moat heavily doped with the first type dopants, and formed on an opposite surface from said conducting layer,

where said moat is configured to provide contact to the conducting layer from the opposite surface; and

a plurality of regions doped with a second type dopants on same surface as said moat.

13. The array of claim 12, wherein said semiconductor substrate includes silicon.