Independently programmable memory segments within a PMOS electrically erasable programmable read only memory array achieved by N-well separation and method therefor

• US 6,504,191 B2
• Filed: 10/08/2001
• Issued: 01/07/2003
• Est. Priority Date: 03/19/1999
• Status: Expired due to Term

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Microchip Technology Incorporated
• Inventors: Spadini, Gianpaolo, Hewitt, Kent D., Gerber, Donald S., Yach, Randy L.
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): MENZ, DOUGLAS M
• Application Number:
  US09/972,563
• Publication Number:
  US 20020014642A1
• Time in Patent Office: 456 Days
• Field of Search: 257/286, 257/339, 257/341, 365/207, 438/227, 438/228
• US Class Current: 257/286
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

An array of P-channel memory cells is separated into independently programmable memory segments by creating multiple, electrically isolated N-wells upon which the memory segments are fabricated. The methods for creating the multiple, electrically isolated N-wells include p-n junction isolation and dielectric isolation.

Claims

1. An electrically erasable programmable read only memory array, comprising:

at least two N-wells in a P-type substrate, wherein said at least two N-wells are electrically isolated from each other and thereby capable of being at different voltages;

a plurality of independently programmable memory segments in each of said at least two N-wells; and

a plurality of independently programmable memory units in each of said plurality of independently programmable memory segments, wherein a one of said plurality of independently programmable memory units is programmable within a respective one of said at least two N-wells.

2. The electrically erasable programmable read only memory array according to claim 1, wherein said one of said plurality of independently programmable memory units is defined as M memory cell columns in common with a memory cell row which are within said respective one of said at least two N-wells.

3. The electrically erasable programmable read only memory array according to claim 2, wherein M is equal to eight.

4. The electrically erasable programmable read only memory array according to claim 2, wherein M is equal to 2ⁿ, where n is a non-negative integer number.

5. The electrically erasable programmable read only memory array according to claim 1, wherein each of said plurality of independently programmable memory segments comprises:

M memory cell columns located within each of said at least two N-wells; and

N memory cell rows located within each of said at least two N-wells.

6. The electrically erasable programmable read only memory array according to claim 5, wherein M is equal to eight and N is equal to 2ⁿ, where n is a positive integer number.

7. The electrically erasable programmable read only memory array according to claim 1, wherein each of said at least two N-wells may be independently biased to different voltage levels.

8. The electrically erasable programmable read only memory array according to claim 1, wherein each of said plurality of independently programmable memory segments further comprises a plurality of select transistors.

9. The electrically erasable programmable read only memory array according to claim 1, wherein each of said plurality of independently programmable memory segments comprises:

a plurality of memory cell columns located within a one of said at least two N-wells; and

a memory cell row located within the one of said at least two N-wells.

10. The electrically erasable programmable read only memory array according to claim 1, wherein a one of said at least two N-wells is biased to approximately ground potential to effect a write operation on a one of said plurality of independently programmable memory segments within said one of said at least two N-wells that is biased to approximately ground potential.

11. The electrically erasable programmable read only memory array according to claim 10, wherein the other ones of said at least two N-wells are biased to a relatively high voltage potential for inhibiting a write operation on each of said plurality of independently programmable memory segments within the other ones of said at least two N-wells.

12. The electrically erasable programmable read only memory array according to claim 1, wherein said one of said plurality of independently programmable memory units may be written to while another one of said plurality of independently programmable memory units in another one of said at least two N-wells may be erased.

13. An electrically erasable programmable read only memory array, comprising:

an N-well in a P-type substrate, said N-well being segmented into a plurality of electrically isolated sub-N-wells that are electrically isolated from each other and thereby capable of being at different voltages;

a plurality of independently programmable memory segments in each of said plurality of sub-N-wells; and

a plurality of independently programmable memory units in each of said plurality of independently programmable memory segments, wherein a one of said plurality of independently programmable memory units is programmable within a respective one of said plurality of sub-N-wells.