Memory cell having a vertical transistor with buried source/drain and dual gates

• US 6,504,201 B1
• Filed: 08/30/2000
• Issued: 01/07/2003
• Est. Priority Date: 07/08/1997
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ahn, Kie Y., Forbes, Leonard, Noble, Wendell P.
• Primary Examiner(s): CRANE, SARA W
• Application Number:
  US09/651,199
• Time in Patent Office: 860 Days
• Field of Search: 257/302, 257/296, 257/304, 257/347, 257/330, 257/331, 257/332
• US Class Current: 257/302
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/488 Word lines

Abstract

An integrated circuit and fabrication method includes a memory cell for a dynamic random access memory (DRAM). Vertically oriented access transistors are formed on semiconductor pillars on buried bit lines. Buried first and second gates are provided for each access transistor on opposing sides of the pillars. Buried word lines extend in trenches orthogonal to the bit lines. The buried word lines interconnect ones of the first and second gates. In one embodiment, unitary gates are interposed and shared between adjacent pillars for gating the transistors therein. In another embodiment, separate split gates are interposed between and provided to the adjacent pillars for separately gating the transistors therein. In one embodiment, the memory cell has a surface area that is approximately 4 F², where F is a minimum feature size. Bulk-semiconductor and semiconductor-on-insulator (SOI) embodiments are provided.

Claims

1. A memory array, comprising:

a substrate;

a plurality of semiconductor pillars that extend outwardly from a working surface of the substrate, each pillar having a plurality of sides including a first side opposite a second side, each pillar having a first source/drain region, a body formed vertically on the first source/drain region, and a second source/drain region formed vertically on the body, the first and second source/drain regions and the body of each pillar forming portions of an access transistor for a memory cell, the pillars being arranged in an array including a plurality of columns separated by first trenches and a plurality of rows separated by second trenches extending orthogonally to the first trenches, the first and second sides of the pillars in each row of pillars facing adjacent second trenches;

a plurality of bit lines, each bit line electrically interconnecting one of the first and the second source/drain regions of each of the pillars in one of the columns of the array; and

a pair of electrically-isolated word lines on opposite sides of each second trench, a first word line of each pair disposed adjacent to the first sides of the pillars in the row of pillars on a first side of the respective second trench to form a first gate for those pillars, a second word line of each pair disposed adjacent to the second sides of the pillars in the row of pillars on a second side of the respective second trench to form a second gate for those pillars, whereby each pillar has first and second gates associated with the first and second sides of that pillar, respectively.

2. The memory array of claim 1, wherein each bit line is disposed between the bodies of the pillars in the respective column of the array and the substrate.

3. The memory array of claim 1, wherein the first source/drain region of each pillar includes a less heavily doped portion and a more heavily doped bit line portion.

4. The memory array of claim 1, wherein each pillar extends outwardly from an insulating portion of the substrate.

5. The memory array of claim 1, wherein each pillar extends outwardly from a semiconductor portion of the substrate.

6. The memory array of claim 1, further comprising a storage capacitor coupled to one of the first and second source/drain regions of each pillar.

7. The memory array of claim 1, further comprising a first insulating layer disposed between the first gate and the first side of each pillar, and a second insulating layer disposed between the second gate and the second side of each pillar.

8. A memory device, comprising:

an array of memory cells having a plurality of columns and a plurality of rows, each cell comprising an access transistor including a semiconductor pillar with body and first and second source/drain regions, and first and second gates disposed adjacent to opposing sides of the pillar;

a plurality of bit lines, each bit line electrically interconnecting one of the first and the second source/drain regions of each of the pillars in one of the columns of the array;

a plurality of first word line pairs, the first word line pairs disposed in first trenches extending orthogonal to the bit lines between adjacent rows of cells, each first word line in the first word line pair electrically isolated from the other first word line in the first word line pair; and

a plurality of second word line pairs, interdigitated with the first word line pairs, the second word line pairs disposed in second trenches extending orthogonal to the bit lines between adjacent rows of cells, each second word line in the second word line pair electrically isolated from the other second word line in the second word line pair, wherein the first gate of each access transistor is addressed by one of the first word lines disposed in the first trench that is adjacent to that access transistor, and the second gate of each access transistor is addressed by one of the second word lines disposed in the second trench adjacent to that access transistor.

9. The memory device of claim 8, wherein each bit line is disposed between the bodies of the pillars in the respective column of the array and a semiconductor substrate.

10. The memory device of claim 8, wherein the first source/drain region of each pillar includes a less heavily doped portion and a more heavily doped bit line portion.

11. The memory device of claim 8, further comprising a substrate, wherein each pillar extends outwardly from an insulating portion of the substrate.

12. The memory device of claim 8, further comprising a substrate, wherein each pillar extends outwardly from a semiconductor portion of the substrate.

13. The memory device of claim 8, wherein each cell further comprises a storage capacitor coupled to one of the first and second source/drain regions of the respective pillar.

14. The memory device of claim 8, wherein adjacent columns of cells are separated by third trenches that extend orthogonally to the first and second trenches.

15. An integrated circuit, comprising:

a substrate;

a pillar of semiconductor material that extends outwardly from a surface of the substrate, and that has an upper surface and a plurality of sides including opposing first and second sides;

an access transistor having a vertically-stacked body and first and second source/drain regions formed within the pillar, and also having a first gate associated with the first side of the pillar and a second gate associated with the second side of the pillar;

a storage capacitor coupled to a first one of the first and second source/drain regions;

a bit line coupled to a second one of the first and second source/drain regions;

a first word line disposed in a first trench extending orthogonal to the bit line on the first side of the pillar, wherein the first word line provides control of the first gate; and

a second word line disposed in a second trench extending orthogonal to the bit line on the second side of the pillar, the second word line being electrically isolated from the first word line, wherein the second word line provides control of the second gate.

16. The integrated circuit of claim 15, wherein the first and second word lines are disposed beneath the upper surface of the pillar, and the storage capacitor is disposed above the upper surface of the pillar.

17. The integrated circuit of claim 15, wherein the bit line is disposed between the body of the access transistor and the substrate.

18. The integrated circuit of claim 15, wherein the first source/drain region of the access transistor includes a less heavily doped portion and a more heavily doped bit line portion.

19. The integrated circuit of claim 15, wherein the first source/drain region of the access transistor includes a less heavily doped portion and a more heavily doped bit line portion.

20. The integrated circuit of claim 15, wherein the pillar also has opposing third and fourth sides, and the third and fourth sides face a third trench and a fourth trench, respectively.

21. A memory array, comprising:

a substrate;

an array of semiconductor pillars that extend outwardly from a working surface of the substrate, each pillar having a plurality of sides including a first side opposite a second side, each pillar having a first source/drain region, a body formed vertically on the first source/drain region, and a second source/drain region formed vertically on the body, the first and second source/drain regions and the body of each pillar forming portions of an access transistor for a memory cell, the array including at least one column including a first pillar, a second pillar separated from the first pillar by a first trench, and a third pillar separated from the second pillar by a second trench, the first and second sides of the second pillar facing the first and second trenches, respectively;

a bit line electrically interconnecting one of the first and the second source/drain regions of the first pillar, the second pillar and the third pillar;

a pair of electrically-isolated first word lines on opposite sides of the first trench, a first word line of the pair of first word lines disposed adjacent to the second side of the first pillar to form a gate for the first pillar, and a second word line of the pair of first word lines disposed adjacent to the first side of the second pillar to form a first gate for the second pillar; and

a pair of electrically-isolated second word lines on opposite sides of the second trench, a first word line of the pair of second word lines disposed adjacent to the second side of the second pillar to form a second gate for the second pillar, and a second word line of the pair of second word lines disposed adjacent to the first side of the third pillar to form a gate for the third pillar.

22. The memory array of claim 21, wherein the bit line is disposed between the bodies of the first pillar, the second pillar and the third pillar, and the substrate.

23. The memory array of claim 21, wherein the first source/drain region of each of the first pillar, the second pillar and the third pillar includes a more heavily doped bit line portion.

24. The memory array of claim 21, further comprising a storage capacitor coupled to one of the first and second source/drain regions of each of the first, second and third pillars.

25. A memory device, comprising:

a substrate;

an array of memory cells arranged in columns and rows on the substrate, adjacent pairs of columns separated by column trenches and adjacent pairs of rows separated by row trenches, each cell comprising a storage capacitor and an access transistor, each access transistor including a semiconductor pillar forming a vertically-stacked body region and first and second source/drain regions, and including first and second gates disposed adjacent to opposing sides of the pillar;

a plurality of bit lines, each bit line electrically interconnecting one of the first and second source/drain regions of each of the pillars in one of the columns of the array; and

a pair of electrically-isolated word lines disposed in each of the row trenches, the first gate of each access transistor controlled by one word line of the pair of word lines disposed in the row trench on one side of the pillar, the second gate of each access transistor controlled by one word line of the pair of word lines disposed in the row trench on the opposing side of the pillar.

26. The memory device of claim 25, wherein each bit line is disposed between the body regions of the pillars in the respective column of the array and the substrate.

27. A memory array, comprising:

a substrate;

a plurality of semiconductor pillars that extend outwardly from a working surface of the substrate, each pillar having a plurality of sides including a first side opposite a second side, each pillar having a first source/drain region, a body formed vertically on the first source/drain region, and a second source/drain region formed vertically on the body, the first and second source/drain regions and the body of each pillar forming portions of an access transistor for a memory cell, the pillars being arranged in an array including a plurality of columns separated by first trenches and a plurality of rows separated by second trenches extending orthogonally to the first trenches, the first and second sides of the pillars in each row of pillars facing adjacent second trenches;

a plurality of bit lines, each bit line electrically interconnecting one of the first and the second source/drain regions of each of the pillars in one of the columns of the array, each bit line being at least partially disposed in the substrate; and

a pair of electrically-isolated word lines on opposite sides of each second trench, a first word line of each pair disposed adjacent to the first sides of the pillars in the row of pillars on a first side of the respective second trench to form a first gate for those pillars, a second word line of each pair disposed adjacent to the second sides of the pillars in the row of pillars on a second side of the respective second trench to form a second gate for those pillars, whereby each pillar has first and second gates associated with the first and second sides of that pillar, respectively.

28. A memory device, comprising:

a substrate;

an array of memory cells arranged in columns and rows on the substrate, adjacent pairs of columns separated by column trenches and adjacent pairs of rows separated by row trenches, each cell comprising a storage capacitor and an access transistor, each access transistor including a semiconductor pillar forming a vertically-stacked body region and first and second source/drain regions, and including first and second gates disposed adjacent to opposing sides of the pillar;

a plurality of bit lines, each bit line electrically interconnecting one of the first and second source/drain regions of each of the pillars in one of the columns of the array, each bit line being at least partially disposed in the substrate; and

a pair of electrically-isolated word lines disposed in each of the row trenches, the first gate of each access transistor controlled by one word line of the pair of word lines disposed in the row trench on one side of the pillar, the second gate of each access transistor controlled by one word line of the pair of word lines disposed in the row trench on the opposing side of the pillar.