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Memory cell having a vertical transistor with buried source/drain and dual gates

  • US 6,504,201 B1
  • Filed: 08/30/2000
  • Issued: 01/07/2003
  • Est. Priority Date: 07/08/1997
  • Status: Expired due to Term
First Claim
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1. A memory array, comprising:

  • a substrate;

    a plurality of semiconductor pillars that extend outwardly from a working surface of the substrate, each pillar having a plurality of sides including a first side opposite a second side, each pillar having a first source/drain region, a body formed vertically on the first source/drain region, and a second source/drain region formed vertically on the body, the first and second source/drain regions and the body of each pillar forming portions of an access transistor for a memory cell, the pillars being arranged in an array including a plurality of columns separated by first trenches and a plurality of rows separated by second trenches extending orthogonally to the first trenches, the first and second sides of the pillars in each row of pillars facing adjacent second trenches;

    a plurality of bit lines, each bit line electrically interconnecting one of the first and the second source/drain regions of each of the pillars in one of the columns of the array; and

    a pair of electrically-isolated word lines on opposite sides of each second trench, a first word line of each pair disposed adjacent to the first sides of the pillars in the row of pillars on a first side of the respective second trench to form a first gate for those pillars, a second word line of each pair disposed adjacent to the second sides of the pillars in the row of pillars on a second side of the respective second trench to form a second gate for those pillars, whereby each pillar has first and second gates associated with the first and second sides of that pillar, respectively.

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