High-voltage transistor with buried conduction layer

• US 6,504,209 B2
• Filed: 06/20/2002
• Issued: 01/07/2003
• Est. Priority Date: 01/24/2001
• Status: Expired due to Term

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Power Integrations Incorporated
• Inventors: Disney, Donald Ray
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): TRAN, LONG K
• Application Number:
  US10/176,325
• Publication Number:
  US 20020153561A1
• Time in Patent Office: 201 Days
• Field of Search: 257/342, 257/104, 257/20, 257/24, 257/27, 257/66, 257/192, 257/213, 257/147, 257/287, 257/346, 257/349, 257/341-343, 257/345, 257/376, 257/348-550, 438/140, 438/342, 438/454, 438/301-306
• US Class Current: 257/342
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A lateral, high-voltage, FET having a low on-resistance and a buried conduction layer comprises a P-type buried layer region within an N-well formed in a P-type substrate. The P-type buried layer region is connected to a drain electrode by a first P-type drain diffusion region that is disposed in the N-well region. The P-type buried layer region is also connected to a second P-type drain diffusion region that extends down from the surface at one end of the PMOS gate region. A P-type source diffusion region, which connects to the source electrode, defines the other end of the gate region.

Claims

1. An extended drain region of a high-voltage field-effect transistor (HVFET) comprising:

a substrate of a first conductivity type;

a well region of a second conductivity type, opposite to the first conductivity type, disposed in the substrate;

a first drain diffusion region of the first conductivity type disposed in the N-well region;

a second drain diffusion region of the first conductivity type disposed in the well region spaced-apart from the first drain diffusion region; and

a buried layer region of the first conductivity type disposed within the well region, the buried layer region being connected to both the first and second drain diffusion regions.

2. The extended drain region of claim 1 wherein the buried layer region comprises a plurality of buried layers.

3. The extended drain region of claim 2 wherein the first drain diffusion region is connected to each of the plurality of buried layers.

4. The extended drain region of claim 3 wherein the second drain diffusion region is connected to each of the plurality of buried layers.

5. The extended drain region of claim 1 wherein the first drain diffusion region has a first surface that adjoins a surface of the substrate.

6. The extended drain region of claim 1 wherein the first conductivity type is P-type and the second conductivity type is N-type.

7. The extended drain region of claim 1 wherein the first drain diffusion region is doped at a slightly higher concentration relative to a doping of the well region.