SOI-structure field-effect transistor and method of manufacturing the same

• US 6,504,213 B1
• Filed: 07/27/2000
• Issued: 01/07/2003
• Est. Priority Date: 07/27/1999
• Status: Active Grant

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Ebina, Akihiko
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Le, Thao P
• Application Number:
  US09/626,606
• Time in Patent Office: 894 Days
• Field of Search: 257/347, 257/240, 257/348, 257/368, 257/396
• US Class Current: 257/347
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78615 with a body contact

Abstract

A dynamic threshold-voltage MOSFET (DTMOS) enables a low power consumption, even during use under conditions of a comparatively high gate voltage. A first contact portion and a gate electrode are placed in electrical contact by a resistance portion. A part of an interconnecting portion is utilized as the resistance portion, by making the width of the part of the interconnecting portion smaller than the width of a remaining part of the interconnecting portion. The forward-direction current flowing through a PN junction formed by a body region and a source region is limited by the resistance portion, even when a comparatively high voltage is applied to the gate electrode. Thus the current between the body region and the source region can be held low. As a result, the power consumption can be reduced, even when the MOS field-effect transistor is used under conditions of a comparatively high gate voltage.

Claims

1. A field-effect transistor formed on a SOI substrate, said SOI-structure field-effect transistor comprising:

a source region, a drain region, a body region, a gate electrode, a gate insulation film, and a resistance portion,

wherein said body region is interposed between said source region and said drain region;

wherein said gate electrode is formed on said body region, with said gate insulation film interposing therebetween;

wherein said gate electrode and said body region are in electrical contact on one side of said gate electrode; and

wherein said gate electrode and said resistance portion are in electrical contact on another side of said gate electrode.

2. The SOI-structure field-effect transistor as defined by claim 1, further comprising:

an extended portion,

wherein said extended portion is formed to extend from an end portion on said another side of said gate electrode; and

wherein a part of said extended portion is employed as said resistance portion, by making the width of the part of said extended portion smaller than the width of a remaining part of said extended portion.

3. The SOI-structure field-effect transistor as defined by claim 1, further comprising:

an extended portion,

wherein said extended portion is formed to extend from an end portion on said other side of said gate electrode; and

wherein a part of said extended portion is employed as said resistance portion, by making the impurity concentration in the part of said extended portion lower than the impurity concentration in a remaining part of said extended portion.

4. The SOI-structure field-effect transistor as defined by claim 1, further comprising:

an extended portion,

wherein said extended portion is formed to extend from an end portion on said other side of said gate electrode; and

wherein a part of said extended portion is employed as said resistance portion, by configuring the part of said extended portion from a polysilicon film alone and forming a remaining part of said extended portion from a polysilicon film and a silicide film.

5. The SOI-structure field-effect transistor as defined by claim 1, further comprising:

an extended portion,

wherein said extended portion is formed to extend from an end portion on said other side of said gate electrode;

wherein said extended portion includes a turning portion; and

wherein said extended portion including said turning portion acts as said resistance portion.

6. The SOI-structure field-effect transistor as defined by claim 1,

wherein the resistance of said resistance portion is greater than the on-resistance of said field-effect transistor.

7. The SOI-structure field-effect transistor as defined by claim 6,

wherein the resistance of said resistance portion is at least ten times the on-resistance of said field-effect transistor.

8. The SOI-structure field-effect transistor as defined by claim 1,

wherein said field-effect transistor is partially depleted.

9. The SOI-structure field-effect transistor as defined by claim 1,

wherein said field-effect transistor is fully depleted.

10. The SOI-structure field-effect transistor as defined by claim 1, wherein said gate electrode is formed on a portion of said body region.

11. The SOI-structure field-effect transistor as defined by claim 1, wherein said resistance portion and said gate electrode comprise the same layer of material.

12. The SOI-structure field-effect transistor as defined by claim 1, further comprising a first gate interconnection in the second gate interconnection.

13. The SOI-structure field-effect transistor as defined by claim 1, wherein said resistance portion is formed over a field oxide film.

14. The SOI-structure field-effect transistor as defined by claim 1, wherein said body region comprises a first conductivity type region and a second conductivity type region, wherein said first conductivity type region has different conductivity than said second conductivity type region.

15. The SOI-structure field-effect transistor as defined by claim 1, wherein the SOI substrate comprises a silicon substrate, a buried oxide film, and a silicon layer, wherein the body region is formed in said silicon layer.

16. A MOS field-effect transistor formed on a SOI substrate, said MOS field-effect transistor comprising:

a source region, a drain region, a body region, a gate electrode, a gate insulation film, a first contact portion, a second contact portion, and a resistance portion,

wherein said body region is interposed between said source region and said drain region and includes a first end portion and a second end portion;

wherein said gate electrode is formed on said body region, with said gate insulation film interposed therebetween, and extends in a direction from said first end portion toward said second end portion;

wherein said first contact portion is formed on said first end portion side;

wherein a gate signal interconnection for transferring a gate signal that is to be input to said gate electrode is connected electrically to said gate electrode via said first contact portion;

wherein said second contact portion is formed on said second end portion side;

wherein said gate electrode is connected electrically to said body region in said second contact portion;

wherein said resistance portion is formed on said first end portion side; and

wherein said gate electrode is connected electrically to said first contact portion through said resistance portion.

17. The SOI-structure MOS field-effect transistor as defined by claim 16,

wherein said resistance portion is comprised within an interconnecting portion;

wherein said interconnecting portion is formed on said first end portion side, and electrically connects said gate electrode and said first contact portion; and

wherein a part of said interconnecting portion is utilized as said resistance portion, by making the width of the part of said interconnecting portion smaller than the width of a remaining part of said interconnecting portion.

18. The SOI-structure MOS field-effect transistor as defined by claim 16,

wherein said resistance portion is comprised within an interconnecting portion;

wherein said interconnecting portion comprises a polysilicon film;

wherein said interconnecting portion is formed on said first end portion side, and electrically connects said gate electrode and said first contact portion; and

wherein a part of said interconnecting portion is utilized as said resistance portion, by making the impurity concentration of the part of said interconnecting layer lower than the impurity concentration of a remaining part of said interconnecting layer.

19. The SOI-structure MOS field-effect transistor as defined by claim 16,

wherein said resistance portion is comprised within an interconnecting portion;

wherein said interconnecting portion is formed on said first end portion side, and electrically connects said gate electrode and said first contact portion; and

wherein a part of said interconnecting portion is utilized as said resistance portion, by forming the part of said interconnecting portion from a polysilicon film alone and forming a remaining part of said interconnecting portion from a polysilicon film and a silicide film.

20. The SOI-structure MOS field-effect transistor as defined by claim 16,

wherein said resistance portion is comprised within an interconnecting portion;

wherein said interconnecting portion is formed on said first end portion side, and electrically connects said gate electrode and said first contact portion; and

wherein a part of said interconnecting portion is utilized as said resistance portion by forming the length of said interconnecting portion is longer than a shortest distance between said first contact portion and said gate electrode.

21. The SOI-structure MOS field-effect transistor as defined by claim 20, comprising:

an element isolation layer disposed in a manner to surround said source region and said drain region,

wherein said interconnecting portion takes a circuitous path on a surface of said element isolation layer and is connected electrically to said first contact portion.

22. The SOI-structure MOS field-effect transistor as defined by claim 16,

wherein the resistance of said resistance portion is greater than the on-resistance of said field-effect transistor.

23. The SOI-structure MOS field-effect transistor as defined by claim 22,

wherein the resistance of said resistance portion is at least ten times the on-resistance of said field-effect transistor.

24. The SOI-structure MOS field-effect transistor as defined by claim 16,

wherein said field-effect transistor is partially depleted.

25. The SOI-structure MOS field-effect transistor as defined by claim 16,

wherein said field-effect transistor is fully depleted.

26. The SOI-structure field-effect transistor as defined by claim 16, wherein said gate electrode is formed on a portion of said body region.

27. The SOI-structure field-effect transistor as defined by claim 16, wherein said resistance portion and said gate electrode comprise the same layer of material.

28. The SOI-structure field-effect transistor as defined by claim 16, wherein said resistance portion is formed over a field oxide film.

29. The SOI-structure field-effect transistor as defined by claim 16, wherein said body region comprises a first conductivity type region and a second conductivity type region, wherein said first conductivity type region has different conductivity than said second conductivity type region.

30. The SOI-structure field-effect transistor as defined by claim 16, wherein the SOI substrate comprises a silicon substrate, a buried oxide film, and a silicon layer, wherein the body region is formed in said silicon layer.