Passive semiconductor device mounted as daughter chip on active semiconductor device

• US 6,504,227 B1
• Filed: 06/29/2000
• Issued: 01/07/2003
• Est. Priority Date: 06/30/1999
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Okumura, Katsuya, Matsunaga, Noriaki, Hayasaka, Nobuo, Matsuo, Mie
• Primary Examiner(s): Flynn, Nathan J.
• Assistant Examiner(s): WILSON, SCOTT R
• Application Number:
  US09/605,433
• Time in Patent Office: 922 Days
• Field of Search: 257/531-535, 257/528, 257/536-538, 257/737-738, 257/750, 257/752, 257/758, 257/762, 438/329, 438/957, 438/382, 438/613, 438/652, 438/118, 438/622, 438/687
• US Class Current: 257/531
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05169 Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/056 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: Y10S 438/957 Making metal-insulator-metal device

Abstract

The present invention provides an integrated circuit, comprising a semiconductor substrate, an active element formed on the side of one main surface of the semiconductor substrate, an insulating region formed on the side of the main surface of the semiconductor substrate by burying an insulating material in a groove having a depth of at least 20 μm, and a passive element formed directly or indirectly on the insulating region. It is desirable for the passive element to be an inductor.

Claims

1. An integrated circuit device, comprising:

a first substrate formed of a semiconductor substrate and having an active element formed on the side of one main surface;

a second substrate having a passive element formed on the side of a first main surface and arranged such that a second main surface opposite to the first main surface faces the main surface of the first substrate; and

an electrode extending through the second substrate from the first main surface to the second main surface so as to electrically connect the passive element to the active element.

2. The integrated circuit device according to claim 1, wherein said passive element is an inductor.

3. The integrated circuit device according to claim 1, wherein said second substrate is formed of a semiconductor substrate having a resistivity higher than the resistivity of the semiconductor substrate constituting said first substrate.

4. The integrated circuit device according to claim 1, wherein said second substrate comprises an insulating substrate.

5. The integrated circuit device according to claim 1, wherein said electrode extending through the second substrate is formed by loading a conductive material in a connecting hole formed in the second substrate.

6. The integrated circuit device according to claim 1, wherein said electrode extending through the second substrate is a projection-like electrode formed on the side of the main surface of said first substrate.

7. The integrated circuit device according to claim 1, wherein said active element and said passive element are electrically connected to each other via the electrode extending through the second substrate and a bump connected to said electrode.

8. The integrated circuit device according to claim 1, wherein an insulating material is loaded between the main surface of said first substrate and the second surface of said second substrate.

9. The integrated circuit device according to claim 1, wherein no passive element is formed on the side of the second main surface.

10. The integrated circuit device according to claim 1, wherein said passive element is formed on the first main surface.

11. A circuit board, comprising:

an insulating layer;

a conductive connecting portion comprising a conductive material prepared by solidifying a conductive past having magnetic properties and extending through the insulating layer; and

a conductive pattern formed on at least one main surface of the insulating layer and connected to the conductive connecting portion.

12. The circuit board according to claim 11, wherein said insulating layer is formed of a compound containing polyimide.