Systems and methods for controlling the charge profile during the commutation event of a synchronous switching transistor in a regulator

• US 6,504,351 B2
• Filed: 02/20/2001
• Issued: 01/07/2003
• Est. Priority Date: 02/20/2001
• Status: Expired due to Term

• Current Assignee: Analog Devices International Unlimited Company (Analog Devices, Inc.)
• Original Assignee: Linear Technology Corporation (Analog Devices, Inc.)
• Inventors: Eagar, Dale R., Seago, John L.
• Primary Examiner(s): Berhane, Adolf Deneke
• Application Number:
  US09/789,960
• Publication Number:
  US 20020113581A1
• Time in Patent Office: 686 Days
• Field of Search: 323/282, 323/284, 323/285
• US Class Current: 323/282
• CPC Class Codes: H02M 1/32 Means for protecting converters other than automatic disconnection
• CPC Class Codes: H02M 3/1582 Buck-boost converters H02M3/1584 takes precedence

Abstract

The present invention provide systems and methods for reducing a reverse recovery current through a body diode in a synchronous switching transistor. An inductor is coupled in the commutation path of the body diode of the synchronous switching transistor. The inductor slows the rate of increase of the reverse recovery current to reduce avalanche effects in the synchronous switching transistor. This reduces the peak reverse recovery current through the body diode of the synchronous switching transistor when the body diode commutates, thereby reducing power dissipation in the main switching transistor. An inductor may be coupled to both switching transistors so that power dissipation is reduced if the regulator is operated as a buck or boost regulator. A diode and a reverse recovery switcher may be coupled to the inductor to transfer energy in the inductor back to the input or output capacitor after the body diode commutates.

Claims

1. A synchronous switching regulator circuit having an input capacitor and an output capacitor, comprising:

first and second switching transistors coupled together and being synchronously switched out of phase by a synchronous switching regulator control circuit;

a main inductor coupled to the first switching transistor; and

a second inductor coupled in a commutation path of a first body diode of the first switching transistor or a second body diode of the second switching transistor that reduces a reverse recovery current in the first or the second body diode.

2. The synchronous switching regulator of claim 1 wherein the second inductor is coupled between the first or the second switching transistor and the main inductor.

3. The synchronous switching regulator of claim 1 wherein the second inductor is coupled between the input capacitor and the first or the second switching transistor.

4. The synchronous switching regulator of claim 1 further comprising:

a diode coupled to the second inductor; and

a recovery switcher coupled to the diode and the input capacitor.

5. The synchronous switching regulator of claim 1 wherein the second inductor is coupled in the commutation path of the second body diode and reduces the reverse recovery current in the second body diode;

and further comprising;

a third inductor coupled in the commutation path of the first body diode that reduces a reverse recovery current in the first body diode.

6. The synchronous switching regulator of claim 5 further comprising:

a diode coupled to the third inductor; and

a recovery switcher coupled to the diode and the input capacitor.

7. The synchronous switching regulator of claim 6 wherein the recovery switcher is a voltage mode non-synchronous switching regulator.

8. The synchronous switching regulator of claim 5 further comprising:

a diode coupled to the second inductor; and

a recovery switcher coupled to the diode and the input capacitor.

9. The synchronous switching regulator of claim 1 further comprising:

a third inductor coupled to the first switching transistor that reduces a reverse recovery current in the second body diode.

10. The synchronous switching regulator of claim 1 wherein the regulator is a buck-boost regulator with third and fourth switching transistors coupled together and to the main inductor.

11. The synchronous switching regulator of claim 10 further comprising:

a third inductor coupled in a commutation path of a body diode of the third or the fourth switching transistor that reduces a reverse recovery current in the body diode of the third or the fourth switching transistor.

12. The synchronous switching regulator of claim 1 wherein the regulator is a buck regulator.

13. The synchronous switching regulator of claim 1 wherein the regulator is a boost regulator.

14. A method for operating a synchronous switching regulator having an input capacitor and an output capacitor, comprising:

switching a first and second synchronous switching transistors out of phase with each other using a switching regulator control circuit to supply current to a load coupled to the output capacitor;

coupling a first inductor to the first and second switching transistors; and

coupling a second inductor in a commutation path of a body diode of the first or the second switching transistor that reduces a reverse recovery current in the body diode of the first or the second switching transistor.

15. The method of claim 14 wherein the second inductor is coupled in a commutation path of the body diode of the first switching transistor and reduces the reverse recovery current in the body diode of the first switching transistor.

16. The method of claim 15 further comprising:

transferring energy stored in the second inductor to the input capacitor after the body diode in the first switching transistor commutates.

17. The method of claim 16 wherein:

transferring energy stored in the second inductor to the input capacitor further comprises coupling a recovery switcher between the second inductor and the input capacitor.

18. The method of claim 15 further comprising:

coupling a third inductor in the commutation path of the body diode of the second switching transistor to reduce a reverse recovery current in the body diode of the second switching transistor.

19. The method of claim 16 further comprising:

transferring energy stored in the third inductor to the input capacitor after the body diode in the second switching transistor commutates.

20. The method of claim 19 wherein transferring energy stored in the third inductor to the input capacitor further comprises coupling a recovery switcher between the third inductor and the input capacitor.

21. The method of claim 14 wherein the second inductor is coupled between the first switching transistor and the input capacitor.

22. The method of claim 14 wherein the second inductor is coupled between the main inductor and the first switching transistor.

23. The method of claim 14 wherein the second inductor is coupled between the main inductor and the second switching transistor.

24. The method of claim 14 wherein the regulator is a buck-boost regulator and further comprising switching third and fourth synchronous switching transistors out of phase using the control circuit.

25. The method of claim 24 further comprising:

coupling a third inductor in a commutation path of a body diode of the third or the fourth switching transistor that reduces a reverse recovery current in the body diode of the third or the fourth switching transistor.

26. A synchronous switching regulator circuit having an input capacitor and an output capacitor, comprising:

means for synchronously switching first and second switching transistors out of phase with each other;

means for storing energy transferred from the input capacitor to the output capacitor; and

inductor means for reducing a reverse recovery current in a body diode of the first or the second switching transistor.

27. The synchronous switching regulator of claim 26 further comprising:

a diode coupled to the means for reducing the reverse recovery current; and

a recovery switcher coupled to the diode and the input capacitor.

28. The synchronous switching regulator of claim 26 further comprising:

means for reducing a reverse recovery current in the body diode of the first switching transistor and the body diode of the second switching transistor.

29. The synchronous switching regulator of claim 28 further comprising:

a diode coupled to the means for reducing the reverse recovery current in the body diode of the first switching transistor and the body diode of the second switching transistor; and

a recovery switcher coupled to the diode and the input capacitor.

30. The synchronous switching regulator of claim 26 wherein the switching regulator is a buck-boost regulator with third and fourth switch transistors coupled together and to the means for storing energy.

31. The synchronous switching regulator of claim 30 further comprising:

means for reducing a reverse recovery current in the body diode of the third or the fourth switching transistor.

32. The synchronous switching regulator of claim 26 wherein the regulator is a buck regulator.

33. The synchronous switching regulator of claim 26 wherein the regulator is a boost regulator.

34. The synchronous switching regulator of claim 26 wherein the inductor means for reducing the reverse recovery current increases the power efficiency of the synchronous switching regulator.

35. The synchronous switching regulator of claim 26 wherein the means for storing energy transferred from the input capacitor to the output capacitor comprises an inductor.

36. A switching regulator circuit having an input node, an output node, and a ground node, the circuit comprising:

a first transistor;

a second transistor;

a first inductor, wherein the first transistor, the second transistor, and the first inductor are coupled in series between the input node and the ground node;

a second inductor coupled between the first transistor and the output node; and

a control circuit for switching the first and second transistors out of phase with each other.

37. The switching regulator circuit of claim 36 further comprising a third inductor coupled in series with the first and second transistors and the first inductor between the input node and the ground node.