Low voltage differential signal (LVDS) input circuit

• US 6,504,403 B2
• Filed: 12/19/2000
• Issued: 01/07/2003
• Est. Priority Date: 12/20/1999
• Status: Expired due to Term

• Current Assignee: Infineon Technologies AG
• Original Assignee: Telefonaktiebolaget LM Ericsson
• Inventors: Thompson, John, Filippi, Raymond, Bängs, Joakim
• Primary Examiner(s): Lam, Tuan T.
• Assistant Examiner(s): Nguyen, Hiep
• Application Number:
  US09/739,263
• Publication Number:
  US 20010004219A1
• Time in Patent Office: 749 Days
• Field of Search: 330/258, 330/254, 330/252, 330/253, 330/259, 327/62, 327/65, 327/63, 327/68, 327/70
• US Class Current: 327/62
• CPC Class Codes: H03F 2203/45418 the CMCL comprising a resistor addition circuit
• CPC Class Codes: H03F 2203/45424 the CMCL comprising a comparator circuit
• CPC Class Codes: H03F 2203/45592 the IC comprising one or more buffer stages other than emitter or source followers between the input signal leads and input leads of the dif amp, e.g. inverter stages
• CPC Class Codes: H03F 3/45085 Long tailed pairs H03F3/45112, H03F3/45139 take precedence
• CPC Class Codes: H03F 3/45556 Controlling the input circuit of the differential amplifier
• CPC Class Codes: H03F 3/4556 Controlling the common emitter circuit of the differential amplifier
• CPC Class Codes: H03K 5/2418 with at least one differential stage
• CPC Class Codes: H04L 25/0276 Arrangements for coupling common mode signals
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end

Abstract

Problems associated with using bipolar differential circuits over a wide common mode voltage range are solved using first and second amplifier circuits 3 and 5, respectively operating over first and second voltage sub-ranges. The low voltage differential signal (LVDS) 1 is applied across a pair of series connected resistors 7 and 9, and to the inputs of the amplifiers 3 and 5. The common mode voltage signal 11 is fed to the inputs of third and fourth amplifiers 15 and 17. The third and fourth amplifiers 15 and 17 ensure that the LVDS receiver has a constant linear transfer characteristic over the differential input signal range and over the full common mode range, especially over the amplifier transition region.

Claims

1. A circuit for receiving a low voltage differential input signal having a common mode voltage range, the circuit comprising:

a first amplifier circuit which operates in a first voltage sub-range of the common mode voltage range;

a second amplifier circuit which operates in a second voltage sub-range of the common mode voltage range; and

a control circuit for controlling the operation of the first and second amplifier circuits so as to provide an output signal over the common mode voltage range of the input signal, and for controlling the summation of the outputs of the first and second amplifiers in an overlapping region of the first and second voltage sub-ranges.

2. A circuit as claimed in claim 1, wherein the first amplifier is a common emitter amplifier circuit.

3. A circuit as claimed in claim 2, wherein the common emitter amplifier circuit is self biased by the input.

4. A circuit as claimed in claim 1, wherein the second amplifier circuit is a common-base amplifier circuit.

5. A circuit as claimed in claim 4, wherein the common base amplifier circuit is connected to receive the input signal, and biased using the common mode voltage of the input signal.

6. A circuit as claimed in claim 5, further comprising a third amplifier circuit for adding a base-emitter voltage to the common mode voltage, and outputting the combined voltage level as the bias voltage to the common-base amplifier circuit.

7. A circuit as claimed in claim 5, wherein the common mode voltage is derived from the mid point of two resistors connected in series across the input signal.

8. A circuit as claimed in claim 1, wherein the control circuit operates the first amplifier during a first voltage sub-range, operates the second amplifier during a second voltage sub-range, and operates both amplifiers in the overlapping region when both amplifiers are turned partially on.

9. A circuit as claimed in claim 8, wherein the control circuit receives the common mode voltage and outputs two current outputs for controlling the operation of the first and second amplifiers.

10. A circuit as claimed in claim 1, wherein the control circuit comprises:

a first transistor (61) biased by the common mode voltage, having its collector connected to a current mirror circuit and its emitter connected to the collector of a second transistor (63);

the current mirror circuit comprising a third transistor (71) having its collector connected to the collector of the first transistor (61), and its emitter connected to a supply voltage, the base of the third transistor (71) being fed back to its collector and connected to the base of a fourth transistor (73) having its emitter connected to a common emitter pair of the second amplifier (5);

the second transistor (63) having its emitter connected to ground via a resistor, and its base connected in common with the bases of fifth and sixth transistors (37, 39);

wherein

the fifth transistor (37) has its collector connected to an emitter pair of the first amplifier (3), and its emitter connected to ground via a resistor;

wherein

the sixth transistor (39) has its collector connected to an emitter pair in the second amplifier (5), and its emitter connected to ground via a resistor.

11. A circuit as claimed in claim 1, wherein the outputs of the amplifiers are capable of driving a differential threshold circuit.

12. A circuit as claimed in claim 1, wherein the circuit is capable of being used in a high speed bipolar integrated circuit process.

13. A method of receiving a low voltage differential input signal having a common mode voltage range, the method comprising the steps of:

providing a first amplifier circuit for operating in a first voltage sub-range of the common mode voltage range;

providing a second amplifier circuit for operating in a second voltage sub-range of the common mode voltage range; and

controlling the operation of the first and second amplifier circuits so as to provide an output signal over the common mode voltage range of the input signal, wherein the output signals from the first and second amplifiers are summed in an overlapping region of the first and second voltage sub-ranges.

14. A method as claimed in claim 13, wherein the first amplifier circuit is a common emitter amplifier circuit.

15. A method as claimed in claim 14, comprising biasing the common emitter amplifier circuit by the input.

16. A method as claimed in any one of claims 13, wherein the second amplifier circuit is a common-base amplifier circuit.

17. A method as claimed in claim 16, further comprising the step of connecting the common-base amplifier circuit to receive the input signal, and biasing it using the common mode voltage of the input signal.

18. A method as claimed in claim 17, wherein a base-emitter voltage is added by a third amplifier circuit to the common mode voltage, and the combined voltage level used to bias the common-base amplifier circuit.

19. A method as claimed in claim 17, wherein the common mode voltage is derived from the mid point of two resistors connected in series across the input signal.

20. A method as claimed in any one of claim 13, wherein the controlling step comprises:

operating the first amplifier during a first voltage sub-range;

operating the second amplifier during a second voltage sub-range; and

,

operating both amplifiers in the overlapping region when both amplifiers are turned on.

21. A method as claimed in claim 20, wherein a fourth amplifier circuit is provided for receiving the common mode voltage and outputting two current outputs for controlling the operation of the first and second amplifiers.