Temperature compensation for internal inductor resistance

• US 6,504,420 B1
• Filed: 11/12/1999
• Issued: 01/07/2003
• Est. Priority Date: 11/12/1998
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Carr, Frank, Vorenkamp, Pieter, Bult, Klaas
• Primary Examiner(s): LE, DINH THANH
• Application Number:
  US09/439,156
• Time in Patent Office: 1,152 Days
• Field of Search: 327/552, 327/362, 327/513, 327/512, 333/174
• US Class Current: 327/513
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 2017/0053 with means to reduce eddy currents
• CPC Class Codes: H01F 2021/125 Printed variable inductor with taps, e.g. for VCO
• CPC Class Codes: H01F 27/34 Special means for preventing or reducing unwanted electric or magnetic effects, e.g. no-load losses, reactive currents, harmonics, oscillations, leakage fields
• CPC Class Codes: H01F 27/40 Structural association with built-in electric component, e.g. fuse
• CPC Class Codes: H01F 27/42 Circuits specially adapted for the purpose of modifying, or compensating for, electric characteristics of transformers, reactors, or choke coils circuits for controlling transformers, reactors or choke coils, for the purpose of obtaining a desired output H02P13/00; impedance networks H03H
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H03B 5/04 Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
• CPC Class Codes: H03B 5/364 the amplifier comprising field effect transistors H03B5/366 takes precedence
• CPC Class Codes: H03D 3/18 by means of synchronous gating arrangements
• CPC Class Codes: H03D 7/161 all the frequency changers being connected in cascade
• CPC Class Codes: H03D 7/18 Modifications of frequency-changers for eliminating image frequencies H03D7/16 takes precedence
• CPC Class Codes: H03F 1/26 Modifications of amplifiers to reduce influence of noise generated by amplifying elements
• CPC Class Codes: H03F 1/3211 : in differential amplifiers
• CPC Class Codes: H03F 2200/111 : the amplifier being a dual or triple band amplifier, e.g. 900 and 1800 MHz, e.g. switched or not switched, simultaneously or not
• CPC Class Codes: H03F 2200/294 : the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/372 : Noise reduction and elimination in amplifier
• CPC Class Codes: H03F 2200/447 : the amplifier being protected to temperature influence
• CPC Class Codes: H03F 2200/63 : the amplifier being suitable for CATV applications
• CPC Class Codes: H03F 2203/45264 : the dif amp comprising frequency or phase stabilisation means
• CPC Class Codes: H03F 2203/45286 : the temperature dependence of a differential amplifier being controlled
• CPC Class Codes: H03F 3/195 : in integrated circuits
• CPC Class Codes: H03F 3/45183 : Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45188 : Non-folded cascode stages
• CPC Class Codes: H03F 3/68 : Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602
• CPC Class Codes: H03F 3/72 : Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• CPC Class Codes: H03G 1/0023 : in emitter-coupled or cascode amplifiers H03G1/0029 takes precedence
• CPC Class Codes: H03G 1/0029 : using FETs
• CPC Class Codes: H03G 3/3052 : in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver H03G3/32, H03G3/34 take precedence
• CPC Class Codes: H03H 11/04 : Frequency selective two-port networks
• CPC Class Codes: H03H 11/1291 : Current or voltage controlled filters
• CPC Class Codes: H03H 11/53 : simulating resistances; simulating resistance multipliers
• CPC Class Codes: H03H 11/54 : Modifications of networks to reduce influence of variations of temperature
• CPC Class Codes: H03H 19/004 : Switched capacitor networks
• CPC Class Codes: H03H 7/25 : comprising an element controlled by an electric or magnetic variable H03H7/27 takes precedence
• CPC Class Codes: H03J 1/0075 : where the receiving frequencies of the stations are stored in a permanent memory, e.g. ROM
• CPC Class Codes: H03J 2200/10 : Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03J 3/04 : Arrangements for compensating for variations of physical values, e.g. temperature
• CPC Class Codes: H03J 3/08 : by varying a second parameter simultaneously with the tuning, e.g. coupling bandpass filter
• CPC Class Codes: H03J 3/185 : with varactors, i.e. voltage variable reactive diodes
• CPC Class Codes: H03L 2207/06 : Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 7/103 : the additional signal being a digital signal
• CPC Class Codes: H03L 7/183 : a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number H03L7/1806 takes precedence
• CPC Class Codes: H03L 7/23 : with pulse counters or frequency dividers

Abstract

A compensation circuit compensates for the variation in the internal resistance of a multi-track inductor over temperature. The compensation circuit includes a dummy inductor that has the same temperature dependent resistance as that of the multi-track inductor that is to be compensated. A first field effect transistor is placed in series with the multi-track inductor that is to be compensated, and a second field effect transistor is placed in series with the dummy inductor, where the gates of the FETs are tied together. A control circuit provides a constant current for the dummy inductor and detects any changes in voltage of the dummy inductor over temperature. The control circuit includes a feedback loop that controls the gate voltage of both first and second FETs so as to compensate for the temperature dependent inductor resistance variations of both the dummy inductor and the multi-track inductor that is to be compensated.

Claims

1. An inductor Q compensation circuit comprising:

a first field effect transistor in series with a spiral inductor filter element;

a dummy inductor;

a constant current and voltage circuit;

a second field effect transistor in series with the dummy inductor acting as a control element to maintain a constant voltage and current in the dummy inductor; and

a differential amplifier having a first input coupled to a voltage reference generated by the constant current and voltage circuit, and a second input coupled to the dummy inductor;

a Q of the spiral inductor filter element is maintained at a constant value by the first field effect transistor having a gate coupled to a gate of the second field effect transistor, the gate of the second field effect transistor coupled to an output of the differential amplifier.

2. The inductor Q compensation circuit of claim 1 wherein the first and second field effect transistors are PMOS devices.

3. The inductor Q compensation circuit of claim 1, wherein the spiral inductor filter element is a multi-track spiral inductor filter element.

4. The inductor Q compensation circuit of claim 3, wherein the dummy inductor is a multi-track dummy inductor.

5. The integrated circuit chip of claim 4, additionally comprising means for sensing the internal resistance oft he second inductor and means responsive to the sensing means for impressing across the second inductor a negative resistance equal to the sensed internal resistance.

6. The integrated circuit chip of claim 5, in which the second inductor has first and second end terminals and the sensing means comprises a transconductance amplifier having positive and negative inputs and having positive and negative outputs, and the impressing means comprises means for connecting the positive input and the negative output to the first end terminal and means for connecting the negative input and the positive output to the second end terminal.

7. The integrated circuit chip of claim 6, in which the filter has a capacitor connected in parallel with the first inductor.

8. An integrated circuit chip comprising:

a filter having an input and an output, the filter having a first inductor with an internal resistance connected to the output;

a second inductor with the same internal resistance as the first inductor;

means connected in series with the second inductor for generating a resistance that varies inversely with temperature to compensate for changes in the internal resistance of the second inductor; and

means for inserting the generated resistance in series with the internal resistance of the first inductor to compensate for changes in the internal resistance of the first inductor;

wherein the generating means comprises a CMOS transistor having a source and a drain connected in series with the secondinductor;

a differential amplifier having an output connected to the gate of the CMOS transistor, one input connected by the second inductor to the drain of the CMOS transistor, and another input connected by a resistor to the source of the CMOS transistor; and

current sources connected to each of the inputs of the CMOS transistor to form a feedback loop that drives the gate of the CMOS transistor to offset changes in the internal resistance of the second inductor by a change in the resistance between the source and drain of the CMOS transistor; and

wherein the inserting means comprises a second CMOS transistor having a source and a drain connected in series with the first inductor and a gate connected to the gate of the CMOS transistor of the generating means to offset changes in the internal resistance of the first inductor by replicating the change in the resistance between the source and drain of the CMOS transistor of the generating means.