Voltage pump and a level translator circuit

• US 6,504,421 B2
• Filed: 08/04/1998
• Issued: 01/07/2003
• Est. Priority Date: 10/15/1993
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Blodgett, Greg A., Merritt, Todd A.
• Primary Examiner(s): Cunningham, Terry D.
• Assistant Examiner(s): TRA, ANH QUAN
• Application Number:
  US09/128,865
• Publication Number:
  US 20020014907A1
• Time in Patent Office: 1,617 Days
• Field of Search: 327/536, 327/390, 327/383, 327/589, 363/60
• US Class Current: 327/536
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type

Abstract

A voltage pump and method of driving a node to an increased potential. A periodic input signal is fed into a precharged small capacitor to create a level shifted periodic intermediate potential at an intermediate node. The intermediate node is a supply node to a level translator circuit. The output of the level translator circuit controls the actuation of a pass transistor. When actuated the pass transistor drives a boosted potential to an output node of the voltage pump circuit. In one embodiment the level translator circuit has a delay element which maintains the deactivation of a pull down portion of the level translator circuit until a pull up portion of the level translator circuit is deactivated. A first diode clamp is used to limit the output of the level translator circuit and the boosted potential to within 1 threshold voltage (of the diode clamp) of each other. A second diode clamp is connected between the terminals of the pass transistor so that the boosted potential does not need to climb above the output potential plus a Vt of the second diode clamp. This in turn limits the gate potential of the transistor through the first diode clamp. In a further embodiment a precharge circuit precharges the first terminal of the transistor to a potential equal to the intermediate potential minus a threshold voltage of the precharge circuit.

Claims

1. A voltage pump configured to increase a value of an input supply potential, comprising:

a first pump circuit responsive to the input supply potential and configured to generate an intermediate potential greater than the input supply potential; and

a second pump circuit responsive to the input supply potential and configured to generate a boosted potential greater than the intermediate potential, the second pump circuit including;

a switching device having a first terminal configured to receive the boosted potential and having a control node;

a capacitor in electrical communication with the control node and configured to charge the control node to a precharge potential;

a first translator portion in electrical communication with the control node and configured to increase the precharge potential by an amount substantially equal to the intermediate potential when activated;

a second translator portion in electrical communication with the control node and configured to drive the potential of the control node toward a reference potential when activated; and

a delay circuit in electrical communication with the second translator portion, said delay circuit configured to interpose a delay between actuation states of said first and said second translator portions.

2. A level translator circuit, comprising:

a first circuit configured to respond to a periodic input potential and configured to accept a periodic supply potential, said first circuit configured to generate a first periodic output potential;

a second circuit configured to respond to said periodic input potential and configured to accept said first periodic output potential and said periodic supply potential, said second circuit configured to generate a second periodic output potential, wherein a maximum amplitude of the first periodic output potential is substantially equal to a maximum amplitude of the periodic supply potential; and

a precharge circuit configured to generate a periodic precharge potential, said second circuit precharged in response to the periodic precharge potential, wherein a maximum amplitude of the second periodic output potential is substantially equal to a sum of a maximum amplitude of the periodic supply potential and the periodic precharge potential.

3. The level translator circuit as specified in claim 2, further comprising a further precharge circuit in electrical communication with said precharge circuit, a control node of said further precharge circuit in electrical communication with an output node of said first circuit.

4. The level translator circuit as specified in claim 3, wherein the first periodic output potential controls said further precharge circuit which, when actuated, precharges a node of said precharge circuit.

5. A level translator circuit, comprising:

a first circuit configured to respond to a periodic input potential and configured to accept a periodic supply potential, said first circuit configured to generate a first periodic output potential;

a second circuit configured to accept said first periodic output potential and to generate a second periodic output potential, wherein a maximum amplitude of the first periodic output potential is substantially equal to a maximum amplitude of the periodic supply potential; and

a precharge circuit configured to generate a periodic precharge potential, said second circuit precharged in response to the periodic precharge potential, wherein a maximum amplitude of the second periodic output potential is substantially equal to a sum of a maximum amplitude of the periodic supply potential and the periodic precharge potential.

6. The level translator circuit as specified in claim 5, wherein said precharge circuit precharges a boosted potential node of said second circuit, said boosted potential node used to generate the second periodic output potential.

7. A level translator circuit, comprising:

a first circuit configured to respond to a periodic input potential and configured to accept a periodic supply potential, said first circuit configured to generate a first periodic output potential;

a second circuit configured to accept said first periodic output potential and to generate a second periodic output potential; and

a precharge circuit configured to generate a periodic precharge potential, said second circuit precharged in response to the periodic precharge potential, wherein a maximum amplitude of the second periodic output potential is substantially equal to a sum of a maximum amplitude of the periodic supply potential and the periodic precharge potential.

8. A level translator circuit, comprising:

a first circuit configured to respond to a periodic input potential and configured to accept a periodic supply potential, said first circuit configured to generate a first periodic output potential;

a second circuit configured to accept said first periodic output potential and to generate a second periodic output potential;

a precharge circuit configured to generate a periodic precharge potential, said second circuit precharged in response to the periodic precharge potential wherein a maximum amplitude of the second periodic output potential is substantially equal to a sum of a maximum amplitude of the periodic supply potential and the periodic precharge potential; and

further precharge circuit in electrical communication with said precharge circuit, a control node of said further precharge circuit in electrical communication with an output node of said first circuit, wherein the first periodic output potential controls said further precharge circuit which, when actuated, precharges a node of said precharge circuit.

9. A circuit, comprising:

a level shifting circuit configured to generate a level shifted periodic potential in response to a first periodic input signal, wherein potentials of pulses of said level shifted periodic potential are shifted in value from potentials of corresponding pulses of said first periodic input signal;

a level translator circuit in electrical communication with said level shifting circuit at a supply node of said level translator circuit, said supply node configured to receive the level shifted periodic potential as a supply potential;

a further level shifting circuit configured to generate a further level shifted periodic potential in response to the first periodic input signal;

a pass device in electrical communication, at a first terminal, with said further level shifting circuit and in electrical communication, at a control terminal, with said level translator circuit, said pass device being configured to drive a potential of a second terminal of said pass device toward a potential of one of the pulses of said further level shifted periodic potential in response to a level translated periodic output potential from said level translator circuit; and

a clamp circuit electrically interposed between the control terminal and the first terminal of said pass device, said clamp circuit configured to clamp a level translated periodic output potential from said level translator circuit to within one clamp circuit threshold voltage of the further level shifted periodic potential.

10. The circuit as specified in claim 9 wherein said level translator circuit is configured to respond to a second periodic input signal to generate said level translated periodic output potential.

11. The circuit as specified in claim 10, further comprising a precharge circuit for precharging the level translator circuit.

12. The circuit as specified in claim 11, wherein said precharge circuit is configured to generate, in response to a third periodic input signal, a precharge potential for precharging said level translator circuit.

14. The circuit as specified in claim 9, wherein potentials of pulses of said further level shifted periodic potential are shifted in value from potentials of corresponding pulses of said first periodic input signal.

15. The circuit as specified in claim 9, further comprising a clamp circuit electrically interposed between a second terminal and the control terminal of said pass device.

16. The circuit as specified in claim 9, further comprising a clamp circuit electrically interposed between the first terminal and a second terminal of said pass device.

19. The circuit as specified in claim 12, wherein a maximum amplitude of the level translated periodic output potential is substantially equal to a sum of a maximum amplitude of the level shifted periodic potential and a maximum amplitude of the precharge potential.

13. A circuit, comprising:

a level shifting circuit configured to generate a level shifted periodic potential in response to a first periodic input signal, wherein potentials of pulses of said level shifted periodic potential are shifted in value from potentials of corresponding pulses of said first periodic input signal;

a level translator circuit in electrical communication with said level shifting circuit at a supply node of said level translator circuit, said supply node configured to receive the level shifted periodic potential as a supply potential, said level translator circuit configured to respond to a second periodic input signal to generate a level translated periodic output potential;

a precharge circuit for precharging the level translator circuit, said precharge circuit configured to generate, in response to a third periodic input signal, a precharge potential for precharging said level translator circuit, wherein a maximum amplitude of the level translated periodic output potential is substantially equal to a sum of a maximum amplitude of the level shifted periodic potential and a maximum amplitude of the precharge potential; and

a clamp circuit configured to clamp the level translated periodic output potential from said level translator circuit to within one clamp circuit threshold voltage of the level shifted periodic potential.

17. A charge pump comprising:

a first level shifting circuit responsive to a first periodic input signal;

a second level shifting circuit responsive to a second periodic input signal;

a level translator circuit coupled to an output of said first level shifting circuit at a supply node of said level translator circuit;

a pass device coupled to said level translator circuit at a control node of said pass device, wherein said pass device is interposed between said second level shifting circuit and an output node of the charge pump, said pass device configured to drive an output potential on said output node of the charge pump toward an output potential from said second level shifting circuit in response to a level translated output potential from said level translator circuit and

a clamp circuit electrically interposed between the control node and a terminal of the second level shifting circuit, said clamp circuit configured to clamp a level translated periodic output potential from said level translator circuit to within one clamp circuit threshold voltage of a level shifted periodic potential generated by the second level shifting circuit.

18. The charge pump as specified in claim 17, wherein said first level shifting circuit provides a periodic supply potential at the supply node of the level translator circuit.

20. A voltage pump for increasing a value of an input supply potential, comprising:

a first circuit portion responsive to the input supply potential and configured to generate an intermediate potential greater than the input supply potential;

a second circuit portion responsive to the input supply potential and configured to generate a boosted potential greater than the input supply potential;

a switching device having a first terminal configured to receive the boosted potential from the second circuit portion and having a gate;

a precharge circuit configured to precharge the first terminal of said switching device to a precharge potential, wherein said precharge circuit comprises;

a transistor in electrical communication with the first terminal of the switching device; and

a buffer circuit electrically interposed between a gate of said transistor and an input of said second circuit portion; and

a third circuit portion responsive to the intermediate potential and configured to generate at the gate of said switching device a gate potential substantially equal to the boosted potential plus said precharge potential.

21. A voltage pump for increasing a value of an input supply potential, comprising:

a first circuit portion responsive to the input supply potential and configured to generate an intermediate potential greater than the input supply potential;

a second circuit portion responsive to the input supply potential and configured to generate a boosted potential greater than the input supply potential;

a switching device having a first terminal configured to receive the boosted potential from the second circuit portion and having a gate;

a precharge circuit configured to precharge the first terminal of said switching device to a precharge potential, wherein said precharge circuit comprises;

a transistor in electrical communication with the first terminal of the switching device;

a buffer circuit electrically interposed between a gate of said transistor and an input of said second circuit portion;

a third circuit portion responsive to the intermediate potential and configured to generate at the gate of said switching device a gate potential substantially equal to the boosted potential plus said precharge potential; and

wherein said buffer circuit is configured to provide a gate potential sufficient to actuate said transistor and to substantially precharge the first terminal of said switching device to the intermediate potential minus a threshold voltage of said transistor which actuated.

22. A method for increasing a value of a supply potential, comprising:

pumping a potential of a first node to an intermediate potential greater than the supply potential;

adjusting a control potential at a control terminal of a switching device and a boosted potential greater than the intermediate potential at a first terminal of said switching device to be within one threshold voltage of one another;

actuating the switching device in response to said control potential;

driving a potential substantially equal to the boosted potential to a second terminal of said switching device in response to said step of actuating;

precharging the first terminal of said switching device to the intermediate potential minus a threshold voltage of a circuit performing said precharging; and

further increasing a value of the potential on said first terminal to the boosted potential.

23. The method as specified in claim 22, further comprising the step of utilizing the intermediate potential as a voltage source for said circuit performing said step of precharging.

24. A voltage pump for increasing a value of an input supply potential, comprising:

a first circuit portion connected to receive the input supply potential and configured to generate an intermediate potential greater than the input supply potential;

a second circuit portion connected to receive the input supply potential and configured to generate a boosted potential greater than the input supply potential;

a switching device having a first terminal connected to receive the boosted potential from the second circuit portion and having a gate;

a third circuit portion connected to receive the intermediate potential and configured to generate a control potential at the gate of said switching device; and

a clamp circuit electrically interposed between the first terminal and the gate, said clamp circuit connected to clamp the control potential and the boosted potential to within a threshold voltage of said clamp circuit.

25. The voltage pump as specified in claim 24, further comprising a precharge circuit in electrical communication with the first terminal of said switching device and responsive to the intermediate potential and configured to precharge the first terminal of the switching device.

26. A method for pumping an input supply potential to a value capable of driving an electrical circuit, comprising:

increasing a value of the input supply potential to provide an intermediate potential greater than the input supply potential;

providing a control potential at a control terminal of a switching device;

increasing a value of a potential of a first terminal of the switching device to create a boosted potential greater than the intermediate potential at the first terminal;

clamping the control potential and the boosted potential to within a threshold voltage of a circuit performing said step of clamping;

actuating the switching device with the control potential; and

precharging the first terminal of the switching device to the intermediate potential minus a threshold voltage of the circuit performing said precharging.

27. The method as specified in claim 26, further comprising coupling the first terminal to a second terminal of the switching device during said actuating.

28. The method as specified in claim 27, further comprising driving the potential of the second terminal toward the boosted potential, wherein the potential driven to the second terminal is capable of driving the electrical circuit.

29. A memory system, comprising:

a monolithic memory device, comprising a voltage pump for increasing a value of an input supply potential, wherein the voltage pump comprises;

a first circuit portion connected to receive the input supply potential and configured to generate an intermediate potential greater than the input supply potential;

a second circuit portion connected to receive the input supply potential and configured to generate a boosted potential greater than the input supply potential;

a switching device having a first terminal connected to receive the boosted potential from the second circuit portion and having a gate;

a third circuit portion connected to receive the intermediate potential and configured to generate a control potential at the gate of said switching device;

a clamp circuit electrically interposed between the first terminal and the gate, said clamp circuit connected to clamp the control potential and the boosted potential to within a threshold voltage of said clamp circuit; and

a processor configured to access the monolithic memory device.

30. A memory system, comprising:

a monolithic memory device comprising a level translator circuit, the level translator comprising;

a first circuit connected to receive to a periodic input potential and connected to receive a periodic supply potential, said first circuit configured to generate a first periodic output potential;

a second circuit connected to receive to said periodic input potential and connected to receive said first periodic output potential and said periodic supply potential, said second circuit configured to generate a second periodic output potential;

a switching device having a first terminal connected to receive the boosted potential from the second circuit portion and having a gate;

a clamp circuit electrically interposed between the first terminal and the gate, said clamp circuit connected to clamp the control potential and the boosted potential to within a threshold voltage of said clamp circuit; and

a processor configured to access the monolithic memory device.

31. A memory system, comprising:

a monolithic memory device, comprising a voltage pump for increasing a value of an input supply potential, wherein the voltage pump comprises;

a first circuit portion connected to receive the input supply potential and configured to generate an intermediate potential greater than the input supply potential;

a second circuit portion connected to receive the input supply potential and configured to generate a boosted potential greater than the input supply potential;

a switching device having a first terminal connected to receive the boosted potential from the second circuit portion and having a gate;

a precharge circuit configured to precharge the first terminal of said switching device to a precharge potential;

a third circuit portion connected to receive the intermediate potential and configured to generate at the gate of said switching device a gate potential substantially equal to the boosted potential plus said precharge potential;

a clamp circuit electrically interposed between the first terminal and the gate, said clamp circuit electrically connected to clamp the control potential and the boosted potential to within a threshold voltage of said clamp circuit; and

a processor configured to access the monolithic memory device.