Feedback clamp circuit to prevent overcharge in compensation capacitor

• US 6,504,435 B1
• Filed: 08/31/2000
• Issued: 01/07/2003
• Est. Priority Date: 08/31/2000
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Martins, Marcus Marchesi
• Primary Examiner(s): Mottola, Steven J.
• Application Number:
  US09/652,080
• Time in Patent Office: 859 Days
• Field of Search: 330/107, 330/292, 330/311, 327/318, 327/319
• US Class Current: 330/292
• CPC Class Codes: H03F 3/3023 with asymmetrical driving of the end stage

Abstract

The present invention provides a dual stage amplifier with a clamping circuit and a methodology, along with a clamping circuit for use with a dual stage amplifier, which eliminate or reduce the overcharging of a compensation capacitor in such a dual stage amplifier. The amplifier includes a first amplifier stage with a first input and a first output, a second amplifier stage having a second input operatively connected to the first output, and a second output. The amplifier further includes a compensation capacitor in electrical communication with the second input and the second output, and a clamping circuit in electrical communication with the second stage, which is adapted to prevent overcharging of the compensation capacitor. The clamping circuit may include a low vgs clamp, a high vgs clamp, and/or a combination low and high vgs clamp, wherein the low vgs clamp is adapted to bias the second input away from a negative supply, and the high vgs clamp is adapted to bias the second input away from a positive supply.

Claims

1. A dual stage amplifier, comprising:

a first amplifier stage having a first stage input and a first stage output;

a second amplifier stage having a second stage input operatively connected to the first stage output, and a second stage output;

a compensation capacitor in electrical communication with the second stage input and the second stage output; and

a clamping circuit in electrical communication with the second stage, and adapted to prevent an overcharging of the compensation capacitor when an imbalance condition exists at the first stage input of the first amplifier stage.

2. The amplifier of claim 1, wherein the clamping circuit includes a low vgs clamp adapted to bias the second stage input away from a negative supply when a voltage at the second stage input falls below a first predetermined level.

3. The amplifier of claim 2, wherein the low vgs clamp is further adapted to sense a voltage drop below the first predetermined level at the second stage input and to inject current from a positive supply into the second stage input to counteract the sensed voltage drop, whereby the second stage input is biased away from the negative supply in response thereto.

4. The amplifier of claim 3, wherein the second amplifier stage comprises a MOS output transistor with a gate operatively connected to the first stage output and a drain operatively connected to the second stage output, wherein the MOS output transistor is adapted to control the second stage output according to the second stage input, and wherein the low vgs clamp comprises a first switching component operatively connected to the gate of the MOS output transistor and adapted to sense a voltage at the second stage input and to provide a signal according to the sensed voltage, and a second switching component operatively connected to the positive supply and the first switching component, and adapted to selectively provide current to the gate of the MOS output transistor according to the signal from the first switching component, whereby the current provided to the gate of the MOS output transistor counteracts a voltage drop at the second stage input.

5. The amplifier of claim 2, wherein the clamping circuit includes a high vgs clamp adapted to bias the second stage input away from a positive supply when a voltage at the second stage input rises above a second predetermined level.

6. The amplifier of claim 5, wherein the high vgs clamp is further adapted to sense a voltage rise above the second predetermined level at the second stage input and to sink current to the negative supply from the second stage input to counteract the sensed voltage rise, whereby the second stage input is biased away from the positive supply in response thereto.

7. The amplifier of claim 6, wherein the second amplifier stage comprises a MOS output transistor with a gate operatively connected to the first stage output and a drain operatively connected to the second stage output, wherein the MOS output transistor is adapted to control the second stage output according to the second stage input, and wherein the high vgs clamp comprises a first switching component operatively connected to the gate of the MOS output transistor and adapted to sense a voltage at the second stage input and to provide a signal according to the sensed voltage, and a second switching component operatively connected to the negative supply and the first switching component and adapted to selectively sink current from the gate of the MOS output transistor according to the signal from the first switching component, whereby the current sinked from the gate of the MOS output transistor counteracts a voltage rise at the second stage input.

8. The amplifier of claim 7, wherein the high vgs clamp is further adapted to sense a voltage rise at the second stage input and to sink current to a negative supply from the second stage input to counteract the sensed voltage rise, whereby the second stage input is biased away from the positive supply in response thereto.

9. The amplifier of claim 8, wherein the second amplifier stage comprises a MOS output transistor with a gate operatively connected to the first stage output and a drain operatively connected to the second stage output, wherein the MOS output transistor is adapted to control the second stage output according to the second stage input, and wherein the high vgs clamp comprises a first switching component operatively connected to the gate of the MOS output transistor and adapted to sense a voltage at the second stage input and to provide a signal according to the sensed voltage, and a second switching component operatively connected to the negative supply and the first switching component and adapted to selectively sink current from the gate of the MOS output transistor according to the signal from the first switching component, whereby the current sinked from the gate of the MOS output transistor counteracts a voltage rise at the second stage input.

10. The amplifier of claim 1, wherein the clamping circuit includes a high vgs clamp adapted to bias the second stage input away from a positive supply when a voltage at the second stage input rises above a predetermined level.

11. A clamp circuit for clamping an input in a dual stage amplifier having a first amplifier stage with a first stage input and a first stage output and a second amplifier stage with a second stage input operatively connected to the first stage output, and a second stage output, the clamp circuit comprising:

a circuit for sensing a voltage at the second stage input and providing a signal according to the sensed voltage; and

a circuit for selectively sourcing or sinking current to the second stage input according to the signal,

wherein the circuit for sensing a voltage at the second stage input and providing a signal according to the sensed voltage comprises a first switching component operatively connected to the second stage input and adapted to sense a voltage at the second stage input and to provide a signal according to the sensed voltage, and wherein the circuit for selectively sourcing or sinking current to the second stage input according to the signal comprises a second switching component operatively connected the first-switching component and one of a positive and a negative supply, and adapted to selectively source or sink current to or from the second stage input, respectively, according to the signal from the first switching component.

12. The clamp circuit of claim 11, wherein the second amplifier stage comprises a MOS output transistor with a gate operatively connected to the first stage output and a drain operatively connected to the second stage output, wherein the MOS output transistor is adapted to control the second stage output according to the second stage input, and wherein the first switching component is operatively connected to the gate of the MOS output transistor and adapted to sense a voltage at the second stage input and to provide a signal according to the sensed voltage, and wherein the second switching component is operatively connected to a positive supply and the first switching component and adapted to selectively provide current to the gate of the MOS output transistor according to the signal from the first switching component, whereby the current provided to the gate of the MOS output transistor counteracts a voltage drop at the second stage input.

13. The clamp circuit of claim 11, wherein the second amplifier stage comprises a MOS output transistor with a gate operatively connected to the first stage output and a drain operatively connected to the second stage output, wherein the MOS output transistor is adapted to control the second stage output according to the second stage input, and wherein the first switching component is operatively connected to the gate of the MOS output transistor and adapted to sense a voltage at the second stage input and to provide a signal according to the sensed voltage, and wherein the second switching component is operatively connected to a negative supply and the first switching component and adapted to selectively sink current from the gate of the MOS output transistor according to the signal from the first switching component, whereby the current sinked from the gate of the MOS output transistor counteracts a voltage rise at the second stage input.

14. In a dual stage amplifier having a first amplifier stage with a first stage input and a first stage output and a second amplifier stage with a second stage input operatively connected to the first stage output, and a second stage output, a method of biasing the second stage input, comprising:

providing a first component in electrical communication with the second stage input;

sensing a voltage at the second stage input using the first component;

generating a signal using the first component according to the sensed voltage at the second stage input;

providing a second component in electrical communication with the first component and the second stage input; and

selectively biasing the second stage input away from one of a positive supply and a negative supply according to the signal from the first component.

15. The method of claim 14, wherein selectively biasing the second stage input away from one of a positive supply and a negative supply according to the signal from the first component comprises selectively sourcing or sinking current to or from the second stage input, respectively, using the second component according to the signal from the first component.

16. The method of claim 15, wherein selectively biasing the second stage input away from one of a positive supply and a negative supply according to the signal from the first component comprises selectively sourcing current to the second stage input using the second component according to the signal from the first component, whereby the second stage input is selectively biased away from the negative supply.

17. The method of claim 16, wherein selectively biasing the second stage input away from one of a positive supply and a negative supply according to the signal from the first component comprises selectively sinking current from the second stage input using the second component according to the signal from the first component, whereby the second stage input is selectively biased away from the positive supply.

18. The method of claim 15, wherein selectively biasing the second stage input away from one of a positive supply and a negative supply according to the signal from the first component comprises selectively sinking current from the second stage input using the second component according to the signal from the first component, whereby the second stage input is selectively biased away from the positive supply.

19. The method of claim 14, wherein the second amplifier stage comprises a MOS output transistor with a gate operatively connected to the first stage output and a drain operatively connected to the second stage output, wherein the MOS output transistor is adapted to control the second stage output according to the second stage input, and wherein the first component is operatively connected to the gate of the MOS output transistor and adapted to sense a voltage at the second stage input and to provide a signal according to the sensed voltage, and wherein the second component is operatively connected to the positive supply and the first switching component and adapted to selectively source or sink current to or from the gate of the MOS output transistor, respectively, according to the signal from the first switching component, whereby the current sourced to or sinked from the gate of the MOS output transistor counteracts a voltage change at the second stage input.

20. A method of preventing overcharging of a compensation capacitor in an amplifier circuit, comprising:

sensing a node voltage associated with the compensation capacitor;

determining whether the sensed node voltage is within a desired range; and

providing compensation to the amplifier according to the sensed voltage if the sensed voltage is outside the desired range,

wherein determining whether the sensed node voltage is within a desired range comprises determining whether the sensed node voltage is greater than a desired maximum voltage, and wherein providing compensation to the amplifier according to the sensed voltage if the sensed voltage is outside the desired range comprises sinking current from the node associated with the compensation capacitor if the sensed node voltage is greater than the desired maximum voltage.

21. A method of preventing overcharging of a compensation capacitor in an amplifier circuit, comprising:

sensing a node voltage associated with the compensation capacitor;

determining whether the sensed node voltage is within a desired range; and

providing compensation to the amplifier according to the sensed voltage if the sensed voltage is outside the desired range,

wherein determining whether the sensed node voltage is within a desired range comprises determining whether the sensed node voltage is less than a desired minimum voltage, and wherein providing compensation to the amplifier according to the sensed voltage if the sensed voltage is outside the desired range comprises sourcing current to the node associated with the compensation capacitor if the sensed node voltage is less than the desired minimum voltage.